Programmable input/output circuit
A programmable input/output (I/O) circuit includes an output buffer coupled between an output signal and an I/O pad and an input comparator coupled between an input signal and the I/O pad. The input comparator includes a first input coupled to the I/O pad. A multiplexor receives a select signal for selecting a first reference voltage from the plurality of reference voltages at a first time and for dynamically selecting a second reference voltage from the plurality of reference voltages at a second time.
1. An input/output (I/O) circuit comprising:
an output buffer having an input coupled to an output signal and an output coupled to an I/O pad, the output buffer having a first reference voltage provided by a reference generator circuit;
an input comparator having a first input coupled to the I/O pad and a second input coupled to a multiplexor coupled to a plurality of reference voltages, the input comparator further comprising an output to provide an input signal,
wherein the multiplexor receives a select signal for selecting a second reference voltage from the plurality of reference voltages at a first time and for dynamically selecting a third reference voltage from the plurality of reference voltages at a second time.
2. The I/O circuit of claim 1 , wherein the select signal for dynamically selecting a third reference voltage from the plurality of reference voltages is provided to the multiplexor without input circuits coupled to the I/O circuit.
3. The I/O circuit of claim 1 , wherein the output buffer is a single input digital buffer coupled to an adjustable reference voltage.
4. The I/O circuit of claim 1 , wherein the input comparator is an operational amplifier in an open loop configuration.
5. The I/O circuit of claim 1 , wherein the plurality of reference voltages are provided from circuits disposed on the same silicon substrate as the I/O circuit.
6. The I/O circuit of claim 1 , wherein at least one of the plurality of reference voltages are provided from circuits disposed on at least one different silicon substrate from the I/O circuit.
7. The I/O circuit of claim 1 , wherein the select signal is generated from a processor circuit.
8. A method for determining a logic state of a signal on an input/output (I/O) pad comprising:
receiving the signal on an input;
comparing a voltage level of the signal to a first reference voltage;
if the voltage level of the signal is less than the first reference voltage, recognizing the signal as a logic LOW; and
if the voltage level of the signal is greater than the first reference voltage, recognizing the signal as a logic HIGH,
wherein the first reference voltage is provided by a reference generator circuit and is selected from a plurality of reference voltages by a select signal and wherein the first reference voltage is selected dynamically during operation of an I/O circuit coupled to the I/O pad, and
wherein the reference generator circuit provides a second reference voltage for an output buffer coupled to the I/O pad and an output signal.
9. The method for determining the logic state of the signal on the I/O pad of claim 8 , wherein the plurality of reference voltages are provided from circuits disposed on a same silicon substrate as the I/O circuit.
10. The method for determining the logic state of the signal on the I/O pad of claim 8 , wherein at least one of the plurality of reference voltages is provided from circuits disposed on a different silicon substrate from the I/O circuit.
11. The method for determining the logic state of the signal on the I/O pad of claim 8 , wherein the plurality of reference voltages are coupled to a multiplexor for receiving the select signal and providing a selected reference voltage to a comparator.
12. The method for determining the logic state of the signal on the I/O pad of claim 11 , wherein the select signal is provided by a processor circuit.
13. The method for determining the logic state of the signal on the I/O pad of claim 12 , wherein the processor circuit is one of a central processing unit, a direct memory access (DMA) controller, a programmable digital circuit, and a fixed function digital circuit.
14. A system comprising:
a processor circuit;
an output buffer having an input coupled to an output signal and an output coupled to an I/O pad, the output buffer having a first reference voltage provided by a reference generator circuit;
an input comparator having a first input coupled to the I/O pad and a second input coupled to a multiplexor coupled to a plurality of reference voltages, the input comparator further comprising an output to provide an input signal,
wherein the multiplexor receives a select signal for selecting a second reference voltage from the plurality of reference voltages at a first time and for dynamically selecting a third reference voltage from the plurality of reference voltages at a second time.
15. The system of claim 14 , wherein the select signal for dynamically selecting a third reference voltage from the plurality of reference voltages is provided to the multiplexor without input circuits coupled to the programmable I/O circuit.
16. The system of claim 15 , wherein the input comparator is an operational amplifier in an open loop configuration.
17. The system of claim 14 , wherein the output buffer is a single input digital buffer coupled to an adjustable reference voltage.
18. The system of claim 17 , wherein the plurality of reference voltages are provided from circuits disposed on a same silicon substrate as the programmable I/O circuit.
19. The system of claim 14 , wherein at least one of the plurality of reference voltages are provided from circuits disposed on different silicon substrates from the programmable I/O circuit.
20. The system of claim 14 , wherein the processing circuit is one of a central processing unit, a direct memory access (DMA) controller, a programmable digital circuit, and a fixed function digital circuit.