IP Library Granted Patent US 11,830,756
Granted Patent B2
US 11,830,756 · App. 16/862,063 · Granted Nov 28, 2023

Temporary die support structures and related methods

Inventors: Francis J. Carney (Mesa, AZ); Michael J. Seddon (Gilbert, AZ)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L21/6835B32B43/006B32B2307/732H01L2221/6834H01L2221/68354H01L2221/68386
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Quick Facts
Patent No.
US 11,830,756
App. No.
16/862,063
Granted
Nov 28, 2023
Kind
B2
Abstract

Implementations of a semiconductor device may include a semiconductor die comprising a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and a temporary die support structure coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The thickness may be between 0.1 microns and 125 microns. The warpage of the semiconductor die may be less than 200 microns.

Claims (24)

1. A semiconductor device comprising:

A single semiconductor die comprising a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and

a temporary die support structure coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof;

wherein the thickness is between 0.1 microns and 125 microns; and

wherein a warpage of the single semiconductor die is less than 200 microns.

2. The device of claim 1 , wherein the warpage of the single semiconductor die is less than 25 microns.

3. The device of claim 1 , wherein a perimeter of the single semiconductor die is rectangular and a size of the single semiconductor die is at least 6 mm by 6 mm.

4. The device of claim 1 , wherein a perimeter of the single semiconductor die is rectangular and a size of the single semiconductor die is 211 mm by 211 mm or smaller.

5. The device of claim 1 , wherein the temporary die support structure is configured to be removable by one of exposure to light, ultrasonic energy, peeling, etching, grinding, or any combination thereof.

6. The device of claim 1 , wherein a perimeter of the single semiconductor die comprises a closed shape.

7. The device of claim 1 , wherein the temporary die support structure comprises a perimeter comprising a closed shape.

8. The device of claim 1 , further comprising a second temporary die support structure coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof.

9. The device of claim 1 , wherein the temporary die support structure comprises two or more layers.

10. A method of forming a die support structure comprising:

temporarily coupling a material with a single semiconductor die:

wherein the single semiconductor die comprises a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and

wherein the material is coupled with one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof; and

reducing a warpage of the single semiconductor die to less than 200 microns through the material.

11. The method of claim 10 , further comprising removing the material using one of light, etching, peeling, ultrasonic energy, grinding, or any combination thereof.

12. The method of claim 11 , further comprising removing the material after bonding the single semiconductor die to one of a substrate, a leadframe, a second semiconductor die, a lead, a redistribution layer, and any combination thereof.

13. The method of claim 10 , wherein the material comprises a perimeter comprising a closed shape.

14. The method of claim 10 , wherein the material is a first portion of material and further comprising:

temporarily coupling a second portion of material with one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof.

15. The method of claim 14 , wherein the second portion of material is a second layer of material coupled over the first portion of material.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL 053613, FRAME 0621 Recorded Aug 17, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064618/0942 →
SECURITY INTEREST Recorded Aug 27, 2020
From: FAIRCHILD SEMICONDUCTOR CORPORATION; SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 053613/0621 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 29, 2020
From: CARNEY, FRANCIS J.; SEDDON, MICHAEL J.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 052528/0513 →
Continuity (1)
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