Supports for thinned semiconductor substrates and related methods

1. A semiconductor substrate comprising:

a uniformly thinned wafer comprising a first side and a second side; and

a support structure separate from a material of the uniformly thinned wafer coupled to the uniformly thinned wafer at a desired location on the first side, the second side, or both the first side and the second side;

wherein the support structure comprises an organic compound;

wherein the support structure comprises a first spoke, a second spoke, and a third spoke; and

wherein an area of the support structure is smaller than an area of either the first side or the second side.

2. The semiconductor substrate of claim 1 , wherein the uniformly thinned wafer is not bonded to a carrier.

3. The semiconductor substrate of claim 1 , wherein each of the first spoke, second spoke, and third spoke are completely separated from one another.

4. The semiconductor substrate of claim 1 , further comprising an edge exclusion region located around a periphery of the uniformly thinned wafer, wherein each of the first spoke, second spoke, and third spoke terminate at an inner edge of the edge exclusion region.

5. The semiconductor substrate of claim 1 , wherein each of the first spoke, second spoke, and third spoke contact at least two adjacent spokes.

6. The semiconductor substrate of claim 1 , wherein the support structure comprises one or more structures, each structure comprising a perimeter comprising a closed shape.

7. The semiconductor substrate of claim 1 , wherein the support structure further comprises a ring coupled around an outer periphery of the uniformly thinned wafer.

8. A semiconductor substrate comprising:

a plurality of support structures comprising an organic compound, the plurality of support structures coupled to a uniformly thinned wafer;

wherein the plurality of support structures have has an area smaller than an area of the surface of the uniformly thinned wafer;

wherein each support structure of the plurality of support structures is separated from an outer edge of the uniformly thinned wafer by a distance; and

wherein each support structure of the plurality of support structures is entirely separated from every other support structure of the plurality of support structures.

9. The semiconductor substrate of claim 8 , wherein each support structure of the plurality of support structures comprises a perimeter substantially in the shape of a circle.

10. The semiconductor substrate of claim 8 , wherein each support structure of the plurality of support structures comprises multiple layers.

11. The semiconductor substrate of claim 8 , wherein each support structure of the plurality of support structures comprises a closed shape.

12. The semiconductor substrate of claim 8 , wherein the support structure is not coupled over a notch comprised on the uniformly thinned wafer.

13. A semiconductor wafer comprising:

a planar semiconductor material comprising a substantially circular perimeter, an edge exclusion region and uniform thickness across a largest planar surface; and

a support structure coupled to the largest planar surface of the planar semiconductor material adjacent to the substantially circular perimeter;

wherein the support structure comprises multiple layers;

wherein the support structure terminates at an inner edge of the edge exclusion region;

wherein the support structure comprises an organic compound; and

wherein an area of the support structure is smaller than an area of the largest planar surface of the planar semiconductor material.

14. The semiconductor wafer of claim 13 , wherein the planar semiconductor material is not bonded to a carrier.

15. The semiconductor wafer of claim 13 , wherein the support structure comprises varying cross sectional shape along a length of the support structure.

16. The semiconductor wafer of claim 15 , wherein the cross sectional shape is a closed shape.

17. The semiconductor wafer of claim 13 , wherein the support structure comprises a cross sectional shape with a highest point along a width of the support structure, the highest point forming a rib.

18. The semiconductor wafer of claim 13 , further comprising one or more semiconductor die, the one or more semiconductor die formed in the planar semiconductor material, and one or more support structures coupled around one of the one or more semiconductor die.

19. The semiconductor wafer of claim 13 , wherein the support structure is not coupled over a notch comprised on the planar semiconductor material.

20. The semiconductor wafer of claim 13 , wherein the support structure comprises two or more intersecting strips.