Memory controller
According to one embodiment, a memory controller includes an encoder, a randomizing circuit, and an interface. The encoder subjects first data received from an external device to error correction coding. The randomizing circuit randomizes second data output from the encoder. The interface transmits third data output from the randomizing circuit to a nonvolatile semiconductor memory and controls write/read of the nonvolatile semiconductor memory. The interface transmits data of a size larger than or equal to a size of a write unit of the nonvolatile semiconductor memory to the nonvolatile semiconductor memory in a write sequence.
1. A memory system comprising:
a nonvolatile memory; and
a controller configured to:
receive first data from a host,
encode the first data to generate an error correction code;
generate second data that includes the first data and the error correction code;
randomize the second data to generate third data;
generate fourth data;
randomize the fourth data to generate fifth data, the size of the fifth data being smaller than the size of the first data;
generate sixth data that includes the third data and the fifth data; the size of the sixth data being equal to the size of a unit of a write operation to the nonvolatile memory; and
transmit the sixth data to the nonvolatile memory.
2. The memory system of claim 1 , wherein
the controller includes a randomizer configured to randomize at least one of the second data and the fourth data.
3. The memory system of claim 2 , wherein
the randomizer is configured to:
receive input data;
generate a pseudo random number sequence; and
generate output data by performing an exclusive- or operation on the input data and the pseudo random number sequence.
4. The memory system of claim 1 , wherein
the first data is received from the host by a plurality of transfers.
5. The memory system of claim 1 , wherein
the fourth data has not been received from the host.
6. The memory system of claim 1 , wherein
all bits of the fourth data are same value.
7. The memory system of claim 1 , wherein
the fifth data includes both “1” data and “0” data.
8. The memory system of claim 1 , wherein
the nonvolatile memory includes a plurality of blocks, each of the plurality of blocks includes a plurality of pages, and
the size of the unit of the write operation is equal to the size of each of the plurality of pages.
9. The memory system of claim 1 , wherein
the nonvolatile memory includes a plurality of planes, each of the plurality of planes includes a plurality of blocks, each of the plurality of blocks includes a plurality of pages, and
the size of the unit of the write operation is the size of each of the plurality of pages multiplied by the number of planes.
10. The memory system of claim 1 , wherein
the nonvolatile memory is a NAND flash memory.
11. A method of controlling a nonvolatile memory, comprising:
receiving first data from a host,
encoding the first data to generate an error correction code;
generating second data that includes the first data and the error correction code;
randomizing the second data to generate third data;
generating fourth data;
randomizing the fourth data to generate fifth data, the size of the fifth data being smaller than the size of the first data;
generating sixth data that includes the third data and the fifth data, the size of the sixth data being equal to the size of a unit of a write operation to the nonvolatile memory; and
transmitting the sixth data to the nonvolatile memory.
12. The method of claim 11 , wherein
the randomizing of at least one of the second data and the fourth data is performed by using a randomizer.
13. The method of claim 12 ; wherein
the randomizer is configured to:
receive input data;
generate a pseudo random number sequence; and
generate output data by performing an exclusive or operation on the input data and the pseudo random number sequence.
14. The method of claim 11 , wherein
the first data is received from the host by a plurality of transfers.
15. The method of claim 11 ; wherein
the fourth data has not been received from the host.
16. The method of claim 11 , wherein
all bits of the fourth data are same value.
17. The method of claim 11 , wherein
the fifth data includes both “1” data and “0” data.
18. The method of claim 11 , wherein
the nonvolatile memory includes a plurality of blocks each of the plurality of blocks includes a plurality of pages, and
the size of the unit of the write operation is equal to the size of each of the plurality of pages.
19. The method of claim 11 , wherein
the nonvolatile memory includes a plurality of planes, each of the plurality of planes includes a plurality of blocks, each of the plurality of blocks includes a plurality of pages, and
the size of the unit of the write operation is equal to the size of each of the plurality of pages multiplied by the number of planes.
20. The method of claim 11 , wherein
the nonvolatile memory is a NAND flash memory.