BSI chip with backside alignment mark
A method includes forming image sensors in a semiconductor substrate. A first alignment mark is formed close to a front side of the semiconductor substrate. The method further includes performing a backside polishing process to thin the semiconductor substrate, forming a second alignment mark on the backside of the semiconductor substrate, and forming a feature on the backside of the semiconductor substrate. The feature is formed using the second alignment mark for alignment.
1. A method comprising:
forming image sensors in a semiconductor substrate, wherein a first alignment mark is formed close to a front side of the semiconductor substrate;
performing a backside polishing process to thin the semiconductor substrate;
forming a second alignment mark on the backside of the semiconductor substrate;
after the second alignment mark is formed, forming deep trench isolation regions extending from a back surface of the semiconductor substrate into the semiconductor substrate; and
forming a feature on the backside of the semiconductor substrate, wherein the feature is formed using the second alignment mark for alignment.
2. The method of claim 1 , wherein the forming the second alignment mark comprises:
etching the semiconductor substrate to form trenches extending from the backside of the semiconductor substrate into the semiconductor substrate.
3. The method of claim 2 , wherein the forming the second alignment mark comprises depositing a dielectric layer to fill the trenches.
4. The method of claim 2 further comprising, before the semiconductor substrate is etched, depositing an additional dielectric layer contacting the back surface of the semiconductor substrate, wherein the trenches penetrate through the additional dielectric layer.
5. The method of claim 1 further comprising:
forming a metal grid on the backside of the semiconductor substrate; and
depositing a dielectric layer on the metal grid; and
forming a third alignment mark, wherein the forming the third alignment mark comprises etching the dielectric layer to form trenches.
6. The method of claim 5 , wherein the trenches have a depth smaller than a thickness of the dielectric layer.
7. The method of claim 1 , wherein the forming the feature comprises:
etching the semiconductor substrate to form a through-opening penetrating through the semiconductor substrate; and
forming a bond pad extending into the through-opening, wherein the bond pad is electrically connected to a metal feature on a front-side of the semiconductor substrate.
8. A method comprising:
forming Shallow Trench Isolation (STI) regions in a semiconductor substrate, wherein the STI regions comprise a first alignment mark;
forming image sensors in the semiconductor substrate;
performing a backside polishing process from a backside of the semiconductor substrate;
forming a second alignment mark in the semiconductor substrate, wherein the second alignment mark is formed by using the first alignment mark for aligning;
etching the semiconductor substrate from the backside of the semiconductor substrate by using the second alignment mark for aligning; and
forming color filters on the backside of the semiconductor substrate.
9. The method of claim 8 , wherein the color filters are formed by using the second alignment mark for aligning.
10. The method of claim 8 further comprising:
forming a dielectric layer on a back surface of the semiconductor substrate; and
forming a third alignment mark extending into the dielectric layer and the semiconductor substrate, wherein the forming the color filters is performed by using the third alignment mark for aligning.
11. The method of claim 8 further comprising forming a plurality of transparent layers on the backside of the semiconductor substrate, wherein the color filters are formed over the plurality of transparent layers.
12. The method of claim 8 further comprising forming micro-lenses on the color filters, wherein the micro-lenses are formed by using the second alignment mark for aligning.
13. The method of claim 8 , wherein after the etching the semiconductor substrate, an STI pad in the STI regions is exposed.
14. The method of claim 13 further comprising etching the STI pad to form openings extending through the STI pad, wherein the openings are formed by using the second alignment mark for aligning.
15. A method comprising:
forming a plurality of Shallow Trench Isolation (STI) regions in a semiconductor substrate, wherein the STI regions comprise:
an STI grid;
a STI pad; and
a first alignment mark;
forming image sensors in the STI grid; and
forming a second alignment mark from a backside of the semiconductor substrate, wherein the second alignment mark is formed by aligning to the first alignment mark.
16. The method of claim 15 further comprising forming a deep trench isolation grid in the semiconductor substrate, wherein the deep trench isolation grid is vertically aligned to the STI grid, and the deep trench isolation grid is formed using the first alignment mark for aligning.
17. The method of claim 15 further comprising forming a deep trench isolation grid in the semiconductor substrate, wherein the deep trench isolation grid is vertically aligned to the STI grid, and the deep trench isolation grid is formed using the second alignment mark for aligning.
18. The method of claim 15 further comprising forming color filters on the backside of the semiconductor substrate, wherein the color filters are formed using the second alignment mark for aligning.
19. The method of claim 15 , wherein the second alignment mark is formed extending into the semiconductor substrate.
20. The method of claim 1 further comprising, after the deep trench isolation regions are formed, forming a third alignment mark extending from the backside of the semiconductor substrate into the semiconductor substrate.