Method for fabricating memory device

1. A method, comprising:

depositing a resistance switching element layer over a bottom electrode layer;

depositing a top electrode layer over the resistance switching element layer;

etching the top electrode layer, the resistance switching element layer, and the bottom electrode layer to form a memory stack;

depositing a first spacer layer over the memory stack;

etching the first spacer layer to form a first spacer extending along a sidewall of the memory stack;

depositing a second spacer layer over the memory stack and the first spacer;

etching the second spacer layer to form a second spacer extending along a sidewall of the first spacer; and

depositing an etch stop layer over and in contact with a top of the second spacer such that a bottom of the etch stop layer is higher than a top of the first spacer, wherein the etch stop layer is spaced apart from the first spacer by a portion of the second spacer.

2. The method of claim 1 , further comprising:

etching a hole in the etch stop layer such that the hole exposes a top surface of the memory stack; and

forming a conductive feature in the hole in the etch stop layer.

3. The method of claim 2 , wherein forming the conductive feature is performed such that the conductive feature is spaced apart from the first spacer by the portion of the second spacer.

4. The method of claim 2 , wherein forming the conductive feature is performed such that a bottom of the conductive feature is higher than the top of the first spacer.

5. The method of claim 2 , wherein etching the hole in the etch stop layer is performed such that the hole further exposes the top of the second spacer.

6. The method of claim 1 , further comprising:

planarizing the top of the second spacer and a top surface of the memory stack prior to depositing the etch stop layer.

7. A method, comprising:

depositing a bottom electrode layer over a first dielectric layer;

depositing a resistance switching element layer over the bottom electrode layer;

depositing a top electrode layer over the resistance switching element layer;

etching the top electrode layer, the resistance switching element layer, and the bottom electrode layer to form a memory stack over the first dielectric layer;

depositing a first spacer layer over the memory stack and the first dielectric layer;

etching the first spacer layer to form a first spacer extending along a sidewall of the memory stack;

depositing a second spacer layer over the memory stack, the first spacer, and the first dielectric layer;

etching the second spacer layer to form a second spacer that has a first portion extending along a sidewall of the first spacer and a second portion extending from the first portion of the second spacer along a top surface of the first dielectric layer, wherein a top surface of the second portion of the second spacer is lower than a bottom surface of the memory stack; and

subsequent to etching the second spacer layer to form the second spacer, depositing a second dielectric layer over and in contact with a top surface of the first portion of the second spacer and the top surface of the second portion of the second spacer.

8. The method of claim 7 , wherein etching the second spacer layer is performed such that the top surface of the first portion of the second spacer is lower than a top surface of the memory stack.

9. The method of claim 7 , wherein etching the second spacer layer is performed such that the top surface of the first portion of the second spacer is higher than a top of the first spacer.

10. The method of claim 7 , further comprising:

planarizing a top surface of the second dielectric layer and a top surface of the memory stack.

11. The method of claim 10 , wherein planarizing the top surface of the second dielectric layer and the top surface of the memory stack is performed such that the top surface of the first portion of the second spacer is planarized.

12. The method of claim 7 , wherein the second portion of the second spacer has a first sub-portion in a cell region and a second sub-portion in a logic region, the memory stack is in the cell region, the first dielectric layer has a first portion in the cell region and a second portion in the logic region, and the second dielectric layer has a first portion in the cell region and a second portion in the logic region, the method further comprising:

etching the second portion of the second dielectric layer, the second sub-portion of the second portion of the second spacer, and the second portion of the first dielectric layer.

13. A method, comprising:

depositing a bottom electrode layer over a dielectric layer;

depositing a resistance switching element layer over the bottom electrode layer;

depositing a top electrode layer over the resistance switching element layer;

etching the top electrode layer, the resistance switching element layer, the bottom electrode layer, and the dielectric layer to form a memory stack over the dielectric layer and a recess in the dielectric layer and surrounding the memory stack;

depositing a first spacer layer over the memory stack and lining the recess of the dielectric layer;

etching the first spacer layer to form a first spacer extending along a sidewall of the memory stack from a bottom surface of the recess;

depositing a second spacer layer over the memory stack and the first spacer; and

etching the second spacer layer to form a second spacer extending along a sidewall of the first spacer.

14. The method of claim 13 , further comprising:

forming a bottom electrode via in the dielectric layer prior to depositing the bottom electrode layer, wherein etching the top electrode layer, the resistance switching element layer, the bottom electrode layer, and the dielectric layer is performed such that the recess in the dielectric layer surrounds the bottom electrode via.

15. The method of claim 13 , wherein etching the first spacer layer is performed such that the first spacer is in contact with a sidewall of the dielectric layer.

16. The method of claim 13 , wherein etching the second spacer layer is performed such that the second spacer extends from the bottom surface of the recess.

17. The method of claim 13 , wherein etching the first spacer layer is performed such that the first spacer exposes a portion of the bottom surface of the recess, and etching the second spacer layer is performed such that the second spacer covers the portion of the bottom surface of the recess.

18. The method of claim 13 , wherein etching the second spacer layer is performed such that the second spacer covers a top of the first spacer.

19. The method of claim 6 , wherein planarizing the top of the second spacer and the top surface of the memory stack is performed such that the top of the second spacer is higher than the top of the first spacer after planarizing the top of the second spacer and the top surface of the memory stack.

20. The method of claim 7 , wherein depositing the second dielectric layer is performed such that the second dielectric layer is further in contact with the memory stack.