MRAM device with octagon profile
A magnetic tunnel junction cell, a cross section with octagon profile, vertically aligned layers of a top electrode, a free layer, a tunneling barrier, a reference layer, a bottom electrode with tapered side surface with a width at an upper surface greater than a width at a lower surface, the reference layer with vertical side surface perpendicular to an upper horizontal surface of the bottom electrode, the free layer and the tunneling barrier, each include a tapered side surface of the same angle, and each include a width at an upper surface less than a width at a lower surface. Forming a bottom electrode of a magnetic tunnel junction cell with a tapered side surface with a width at an upper surface greater than a width at a lower surface, forming a reference layer with vertical side surface perpendicular to an upper surface of the bottom electrode.
1. A semiconductor device comprising:
a magnetic tunnel junction (MTJ) stack, wherein a cross section of the MTJ stack comprises an octagon profile;
the MTJ stack comprises vertically aligned layers of a top electrode, a free layer, a tunneling barrier, a reference layer and a bottom electrode;
the bottom electrode comprises a tapered side surface comprising a width at an upper surface of the bottom electrode greater than a width at a lower surface of the bottom electrode;
the reference layer comprises a vertical side surface perpendicular to an upper horizontal surface of the bottom electrode; and
the top electrode, the free layer and the tunneling barrier, each comprise a tapered side surface of the same angle, and each comprise a width at an upper surface less than a width at a lower surface.
2. The semiconductor device according to claim 1 , further comprising:
a first encapsulation layer surrounding vertical side surfaces of the reference layer.
3. The semiconductor device according to claim 1 , further comprising:
a second encapsulation layer surrounding vertical side surfaces of the top electrode, the free layer and the tunneling barrier.
4. The semiconductor device according to claim 1 , further comprising:
a first inter-layer dielectric surrounding the bottom electrode;
a second inter-layer dielectric surrounding the reference layer; and
a third inter-layer dielectric surrounding the top electrode, the free layer and the tunneling barrier.
5. A semiconductor device comprising:
a magnetic tunnel junction (MTJ) stack comprising vertically aligned layers of a top electrode, a free layer, a tunneling barrier, a reference layer and a bottom electrode, wherein a cross section of the vertically aligned layers the MTJ stack comprises an octagon profile, wherein the top electrode, the free layer and the tunneling barrier each comprise a tapered side surface of the same angle, and each comprise a width at an upper surface less than a width at a lower surface; and
a first encapsulation layer surrounding vertical side surfaces of the reference layer.
6. The semiconductor device according to claim 5 , further comprising:
the bottom electrode comprises a tapered side surface comprising a width at an upper surface of the bottom electrode greater than a width at a lower surface of the bottom electrode.
7. The semiconductor device according to claim 5 , further comprising:
the reference layer comprises a vertical side surface perpendicular to an upper horizontal surface of the bottom electrode.
8. The semiconductor device according to claim 5 , further comprising:
a second encapsulation layer surrounding vertical side surfaces of the top electrode, the free layer and the tunneling barrier.
9. The semiconductor device according to claim 5 , further comprising:
a first inter-layer dielectric surrounding the bottom electrode;
a second inter-layer dielectric surrounding the reference layer; and
a third inter-layer dielectric surrounding the top electrode, the free layer and the tunneling barrier.
10. A semiconductor device comprising:
a magnetic tunnel junction (MTJ) stack comprising vertically aligned layers of a top electrode, a free layer, a tunneling barrier, and a reference layer, wherein the top electrode, the free layer and the tunneling barrier each comprise a tapered side surface of the same angle, and each comprise a width at an upper surface less than a width at a lower surface, and wherein the reference layer comprises a vertical side surface perpendicular to an upper horizontal surface of a bottom electrode.
11. The semiconductor device according to claim 10 , further comprising:
a bottom electrode comprising a tapered side surface and a width at an upper surface of the bottom electrode greater than a width at a lower surface of the bottom electrode.
12. The semiconductor device according to claim 10 , further comprising:
a second encapsulation layer surrounding vertical side surfaces of the top electrode, the free layer and the tunneling barrier.
13. The semiconductor device according to claim 10 , further comprising:
a first inter-layer dielectric surrounding a bottom electrode;
a second inter-layer dielectric surrounding a reference layer, and
a third inter-layer dielectric surrounding the top electrode, the free layer and the tunneling barrier.