Magnetoresistive random access memory and method for fabricating the same

1. A method for fabricating semiconductor device, comprising:

forming a magnetic tunneling junction (MTJ) stack on a substrate;

removing part of the MTJ stack;

forming a first cap layer on a sidewall of the MTJ stack; and

removing portions of the first cap layer and portions of the MTJ stack to form a first MTJ and a second MTJ.

2. The method of claim 1 , wherein the MTJ stack comprises a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer, the method comprising:

forming a top electrode on the MTJ stack;

removing the top electrode and the free layer;

forming the first cap layer on sidewalls of the top electrode and the free layer; and

removing the first cap layer, the barrier layer, and the pinned layer to form the first MTJ and the second MTJ.

3. The method of claim 2 , wherein the free layer comprises:

a first free layer on the barrier layer;

a stop layer on the first free layer; and

a second free layer on the stop layer.

4. The method of claim 3 , further comprising:

forming a hard mask on the top electrode;

removing the hard mask, the top electrode and the second free layer; and

forming the first cap layer on sidewalls of the top electrode, the second free layer, the stop layer, and the first free layer and a top surface of the barrier layer.

5. The method of claim 4 , further comprising:

forming a second cap layer on the hard mask and the first cap layer; and

removing the second cap layer, the first cap layer, the hard mask, the barrier layer, and the pinned layer to form a first spacer and a second spacer adjacent to the free layer and the top electrode.

6. The method of claim 5 , wherein a sidewall of the first spacer is aligned with a sidewall of the barrier layer.

7. The method of claim 5 , wherein a sidewall of the second spacer is aligned with a sidewall of the barrier layer.

8. The method of claim 5 , further comprising:

performing an oxidation process to form a third spacer on sidewalls of the barrier layer and the pinned layer; and

forming a third cap layer on the top electrode, the second spacer, and the third spacer.

9. The method of claim 8 , further comprising performing the oxidation process to form a fourth spacer on the third spacer.

10. The method of claim 8 , wherein the third cap layer comprises a hydrogen-free dielectric layer.

11. The method of claim 1 , further comprising performing an oxidation process to form the first cap layer.

12. A semiconductor device, comprising:

a magnetic tunneling junction (MTJ) on a substrate, wherein the MTJ comprises:

a pinned layer on the substrate;

a barrier layer on the pinned layer; and

a free layer on the barrier layer, wherein a critical dimension of a bottom surface of the free layer is different from a critical dimension of a top surface of the barrier layer.

13. The semiconductor device of claim 12 , wherein a width of the free layer is less than a width of the pinned layer.

14. The semiconductor device of claim 12 , further comprising a reference layer between the barrier and the pinned layer.

15. The semiconductor device of claim 14 , wherein a width of the free layer is less than a width of the reference layer.

16. The semiconductor device of claim 14 , wherein the free layer and the reference layer comprise same material.

17. The semiconductor device of claim 14 , further comprising:

a first spacer on sidewalls of the free layer;

a second spacer on the first spacer; and

a third spacer on sidewalls of the reference layer and pinned layer.

18. The semiconductor device of claim 17 , wherein the first spacer comprises a L-shape.

19. The semiconductor device of claim 17 , further comprising a cap layer on sidewalls of the third spacer.

20. The semiconductor device of claim 19 , wherein the cap layer comprises a hydrogen-free dielectric layer.