IP Library Granted Patent US 11,968,906
Granted Patent B2
US 11,968,906 · App. 16/882,552 · Granted Apr 23, 2024

Semiconductor device and method for fabricating the same

Inventors: Jin-Yan Chiou (Tainan, TW); Wei-Chuan Tsai (Changhua County, TW); Hsin-Fu Huang (Tainan, TW); Yen-Tsai Yi (Tainan, TW); Hsiang-Wen Ke (Kaohsiung, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H10N50/80G11C11/161H10N50/01H01F10/3254H01F41/32H10N50/85
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Quick Facts
Patent No.
US 11,968,906
App. No.
16/882,552
Granted
Apr 23, 2024
Kind
B2
Abstract

A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a contact hole in the first IMD layer; forming a bottom electrode layer in the contact hole; forming a magnetic tunneling junction (MTJ) stack on the bottom electrode layer; and removing the MTJ stack and the bottom electrode layer to form a MTJ on a bottom electrode. Preferably, the bottom electrode protrudes above a top surface of the first IMD layer.

Claims (20)

1. A semiconductor device, comprising:

a first inter-metal dielectric (IMD) layer on a substrate;

a bottom electrode in the first IMD layer and protruding above a top surface of the first IMD layer;

a liner directly contacting sidewalls and a bottom surface of the bottom electrode, wherein a bottom surface width in a cross section view of the liner is less than a top surface width in a cross section view of the bottom electrode, the liner comprises a U-shape having a first vertical portion, a second vertical portion, and a horizontal portion connecting the first vertical portion and the second vertical portion, and the first vertical portion and the second vertical portion are not extended to directly contact a top surface of the first IMD layer;

a magnetic tunneling junction (MTJ) on the bottom electrode, wherein a bottom surface width in the cross section view of the bottom electrode is less than a bottom surface width in a cross section view of the MTJ, sidewalls of the MTJ are aligned with sidewalls of the first vertical portion and the second vertical portion, and the MTJ comprises:

a pinned layer on and directly contacting the bottom electrode;

a barrier layer on the pinned layer;

a free layer on the barrier layer; and

a top electrode on the MTJ.

2. The semiconductor device of claim 1 , further comprising:

a second IMD layer on the substrate;

a metal interconnection in the second IMD layer;

the first IMD layer on the second IMD layer; and

the bottom electrode on the metal interconnection.

3. The semiconductor device of claim 2 , further comprising the liner between the bottom electrode and the metal interconnection.

4. The semiconductor device of claim 3 , wherein the liner and the bottom electrode comprise different materials.

5. The semiconductor device of claim 3 , wherein the liner comprises titanium (Ti).

6. The semiconductor device of claim 3 , wherein the liner comprises a U-shape.

7. The semiconductor device of claim 1 , wherein the bottom electrode comprises titanium nitride (TiN).

8. The semiconductor device of claim 1 , wherein the bottom electrode is a single piece.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2020
From: CHIOU, JIN-YAN; TSAI, WEI-CHUAN; HUANG, HSIN-FU; YI, YEN-TSAI; KE, HSIANG-WEN
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 052740/0506 →
Priority Claims (1)
CN 202010354013.4 · Apr 29, 2020 · national
Continuity (1)
Related Publication 20210343931A1 · Nov 4, 2021
Cited By (3)
US 12,279,536 US 12,389,807 US 12,400,698