Gap patterning for metal-to-source/drain plugs in a semiconductor device

1. A method for manufacturing a semiconductor device, the method comprising:

forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain;

creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain;

filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain;

forming a gap in the metal layer to create a first metal contact and a second metal contact,

wherein the first metal contact is electrically coupled to the first source/drain and the second metal contact is electrically coupled to the second source/drain, and

wherein the gap separates the first metal contact from the second metal contact by less than nineteen nanometers; and

filling the gap with a same material used for the first dielectric layer.

2. The method of claim 1 , further comprising:

forming a second dielectric layer on top of the first dielectric layer, the first metal contact, and the second metal contact;

creating a first via in the second dielectric layer to expose a portion of the first metal contact;

creating a second via in the second dielectric layer to expose a portion of the second metal contact;

filling the first via to create a third metal contact that is electrically coupled to the first metal contact; and

filling the second via to create a fourth metal contact that is electrically coupled to the second metal contact.

3. The method of claim 1 , wherein creating the opening in the mask layer and the first dielectric layer comprises:

forming a photoresist layer above portions of the mask layer and the first dielectric layer; and

performing one or more etching operations to remove portions of the mask layer and the first dielectric layer other than the portions of the mask layer and the first dielectric layer formed below the photoresist layer,

wherein the removed portions of the mask layer and the first dielectric layer correspond to the opening that exposes portions of the first source/drain and the second source/drain.

4. The method of claim 1 , further comprising:

polishing the metal layer to be substantially planar with the first dielectric layer and to remove the mask layer, prior to forming the gap in the metal layer.

5. The method of claim 1 , wherein forming the gap in the metal layer comprises:

forming a photoresist layer above portions of the metal layer and the first dielectric layer except a portion of the metal layer associated with the gap; and

performing one or more etching operations to remove the portion of the metal layer,

wherein the removed portion of the metal layer corresponds to the gap in the metal layer.

6. The method of claim 1 , wherein forming the gap in the metal layer comprises:

forming a bottom layer on top of the metal layer and the first dielectric layer;

forming a middle layer on top of the bottom layer;

forming a photoresist layer above portions of the metal layer, the first dielectric layer, the bottom layer, and the middle layer, except a portion of the metal layer associated with the gap; and

performing one or more etching operations to remove the portion of the metal layer, the photoresist layer, the bottom layer, and the middle layer,

wherein the removed portion of the metal layer corresponds to the gap in the metal layer.

7. The method of claim 1 , wherein creating the opening in the mask layer and the first dielectric layer comprises:

forming a bottom layer on top of the mask layer;

forming a middle layer on top of the bottom layer;

forming a photoresist layer above portions of the first dielectric layer, the mask layer, the bottom layer, and the middle layer; and

performing one or more etching operations to remove the photoresist layer, the bottom layer, the middle layer, and portions of the mask layer and the first dielectric layer other than the portions of the mask layer and the first dielectric layer formed below the photoresist layer,

wherein the removed portions of the mask layer and the first dielectric layer correspond to the opening that exposes portions of the first source/drain and the second source/drain.

8. The method of claim 1 , wherein the semiconductor device includes a substrate with fins and an insulation layer formed on top of the substrate,

wherein one or more first fins electrically couple to the first source/drain and one or more second fins electrically couple to the second source/drain.

9. A device, comprising:

one or more memories; and

one or more processors, coupled to the one or more memories, configured to:

form a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain;

create an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain;

fill the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain;

form a gap in the metal layer to create a first metal contact and a second metal contact,

wherein the first metal contact is electrically coupled to the first source/drain and the second metal contact is electrically coupled to the second source/drain, and

wherein the gap separates the first metal contact from the second metal contact by less than nineteen nanometers; and

fill the gap with a same material used for the first dielectric layer.

10. The device of claim 9 , wherein the one or more processors, to create the opening in the mask layer and the first dielectric layer, are configured to:

form a photoresist layer above portions of the mask layer and the first dielectric layer; and

perform one or more etching operations to remove portions of the mask layer and the first dielectric layer other than the portions of the mask layer and the first dielectric layer formed below the photoresist layer,

wherein the removed portions of the mask layer and the first dielectric layer correspond to the opening that exposes portions of the first source/drain and the second source/drain.

11. The device of claim 9 , wherein the one or more processors are further configured to:

polish the metal layer to be substantially planar with the first dielectric layer and to remove the mask layer, prior to forming the gap in the metal layer.

12. The device of claim 9 , wherein the one or more processors, to form the gap in the metal layer, are configured to:

form a photoresist layer above portions of the metal layer and the first dielectric layer except a portion of the metal layer associated with the gap; and

perform one or more etching operations to remove the portion of the metal layer,

wherein the removed portion of the metal layer corresponds to the gap in the metal layer.

13. The device of claim 9 , wherein the one or more processors, to form the gap in the metal layer, are configured to:

form a bottom layer on top of the metal layer and the first dielectric layer;

form a middle layer on top of the bottom layer;

form a photoresist layer above portions of the metal layer, the first dielectric layer, the bottom layer, and the middle layer, except a portion of the metal layer associated with the gap; and

perform one or more etching operations to remove the portion of the metal layer, the photoresist layer, the bottom layer, and the middle layer,

wherein the removed portion of the metal layer corresponds to the gap in the metal layer.

14. The device of claim 9 , wherein the one or more processors, to create the opening in the mask layer and the first dielectric layer, are configured to:

form a bottom layer on top of the mask layer;

form a middle layer on top of the bottom layer;

form a photoresist layer above portions of the first dielectric layer, the mask layer, the bottom layer, and the middle layer; and

perform one or more etching operations to remove the photoresist layer, the bottom layer, the middle layer, and portions of the mask layer and the first dielectric layer other than the portions of the mask layer and the first dielectric layer formed below the photoresist layer,

wherein the removed portions of the mask layer and the first dielectric layer correspond to the opening that exposes portions of the first source/drain and the second source/drain.

15. A non-transitory computer-readable medium storing a set of instructions, the set of instructions comprising:

one or more instructions that, when executed by one or more processors of a device, cause the device to:

form a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain;

create an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain;

fill the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain;

form a gap in the metal layer to create a first metal contact and a second metal contact,

wherein the first metal contact is electrically coupled to the first source/drain and the second metal contact is electrically coupled to the second source/drain, and

wherein the gap separates the first metal contact from the second metal contact by less than nineteen nanometers; and

fill the gap with a same material used for the first dielectric layer.

16. The non-transitory computer-readable medium of claim 15 , wherein the one or more instructions, that cause the device to create the opening in the mask layer and the first dielectric layer, cause the device to:

form a photoresist layer above portions of the mask layer and the first dielectric layer; and

perform one or more etching operations to remove portions of the mask layer and the first dielectric layer other than the portions of the mask layer and the first dielectric layer formed below the photoresist layer,

wherein the removed portions of the mask layer and the first dielectric layer correspond to the opening that exposes portions of the first source/drain and the second source/drain.

17. The non-transitory computer-readable medium of claim 15 , wherein the one or more instructions further cause the device to:

polish the metal layer to be substantially planar with the first dielectric layer and to remove the mask layer, prior to forming the gap in the metal layer.

18. The non-transitory computer-readable medium of claim 15 , wherein the one or more instructions, that cause the device to form the gap in the metal layer, cause the device to:

form a photoresist layer above portions of the metal layer and the first dielectric layer except a portion of the metal layer associated with the gap; and

perform one or more etching operations to remove the portion of the metal layer,

wherein the removed portion of the metal layer corresponds to the gap in the metal layer.

19. The non-transitory computer-readable medium of claim 15 , wherein the one or more instructions, that cause the device to form the gap in the metal layer, cause the device to:

form a bottom layer on top of the metal layer and the first dielectric layer;

form a middle layer on top of the bottom layer;

form a photoresist layer above portions of the metal layer, the first dielectric layer, the bottom layer, and the middle layer, except a portion of the metal layer associated with the gap; and

perform one or more etching operations to remove the portion of the metal layer, the photoresist layer, the bottom layer, and the middle layer,

wherein the removed portion of the metal layer corresponds to the gap in the metal layer.

20. The non-transitory computer-readable medium of claim 15 , wherein the one or more instructions, that cause the device to create the opening in the mask layer and the first dielectric layer, cause the device to:

form a bottom layer on top of the mask layer;

form a middle layer on top of the bottom layer;

form a photoresist layer above portions of the first dielectric layer, the mask layer, the bottom layer, and the middle layer; and

perform one or more etching operations to remove the photoresist layer, the bottom layer, the middle layer, and portions of the mask layer and the first dielectric layer other than the portions of the mask layer and the first dielectric layer formed below the photoresist layer,

wherein the removed portions of the mask layer and the first dielectric layer correspond to the opening that exposes portions of the first source/drain and the second source/drain.