Power semiconductor device with a series connection of two devices
A device includes a heterojunction device, a unipolar power transistor operatively connected in series with said hetero junction device; an external control terminal for driving said unipolar power transistor and said heterojunction device; and an interface unit having a plurality of interface terminals. A first interface terminal is operatively connected to an active gate region of the heterojunction device and a second interface terminal is operatively connected to said external control terminal. The heterojunction device includes a threshold voltage less than a threshold voltage of the unipolar power transistor, wherein the threshold voltage of the heterojunction device is less than a blocking voltage of the unipolar power transistor.
1. A device comprising:
a heterojunction device comprising a first heterojunction terminal, a second heterojunction terminal and a heterojunction gate terminal operatively connected to an active gate region;
a unipolar power transistor operatively connected in series with said heterojunction device;
an interface unit comprising a first interface terminal and a second interface terminal, wherein the first interface terminal is operatively connected to the heterojunction gate terminal, and wherein the second interface terminal is configured as a gate switching terminal,
wherein the interface unit controllably increases the threshold voltage of the heterojunction device, when the threshold voltage relates to a potential applied to the second interface terminal,
wherein a threshold voltage of said heterojunction device is less than a threshold voltage of said unipolar power transistor and is less than a blocking voltage of said unipolar power transistor,
wherein the unipolar power transistor is a silicon based power metal oxide semiconductor field effect transistor (MOSFET), the unipolar power transistor comprising a first silicon terminal, a second silicon terminal and a third silicon gate terminal, and wherein the second silicon terminal is operatively connected to the first heterojunction terminal and wherein the silicon gate terminal is operatively connected to the second interface terminal,
wherein said heterojunction device is a III-nitride semiconductor based heterojunction device, and wherein said active gate region of the heterojunction device comprises a p-type gallium nitride (pGaN) material, and
wherein the heterojunction device and the unipolar power transistor are operable using a single control signal during switching of the device.
2. The device according to claim 1 , wherein an absolute value of the gate threshold voltage of the heterojunction device is less than a blocking voltage of said unipolar power transistor.
3. The device according to claim 1 where the threshold voltage of the heterojunction device related to the potential applied to the second interface terminal is about the same or close to the threshold voltage of the unipolar power transistor.
4. The device according to claim 1 , wherein the interface unit increases an operating voltage range of the heterojunction device when the operating voltage range relates to a potential applied to the second interface terminal.
5. The device according to claim 1 , wherein the interface unit is monolithically integrated with the heterojunction device and comprises at least one heterojunction transistor.
6. The device according to claim 1 , further comprising a slew rate control unit in series with the interface unit, wherein said slew rate control unit is controllably adjusts at least one of a speed (slew rate) and a delay time during switching of the heterojunction device.
7. The device according to claim 1 , wherein the threshold voltage of the heterojunction device is greater than or equal to zero volts.
8. The device according to claim 1 , wherein the threshold voltage of the heterojunction device is less than zero volts.
9. The device according to claim 1 ,
wherein said heterojunction device further comprises:
a substrate;
an active heterojunction transistor formed on the substrate in a first dimension, the active heterojunction transistor comprising:
a III-nitride semiconductor region comprising a first heterojunction comprising an active two dimensional carrier gas;
the first terminal operatively connected to the III-nitride semiconductor region;
the second terminal laterally spaced from the first terminal in a second dimension and operatively connected to the III-nitride semiconductor region;
the heterojunction gate terminal connected to at least part of the active gate region formed over the III-nitride semiconductor region and between the first terminal and the second terminal.
10. The device according to claim 1 , wherein the active gate region of the heterojunction device comprises a plurality of pGaN islands separated in a third dimension, wherein the threshold voltage of the heterojunction device is related to a size of a separation between adjacent pGaN islands, and wherein the third dimension is perpendicular to the second dimension.
11. The device of claim 10 , wherein during an on-state forward conduction mode at least one of:
a potential applied to the second terminal of the heterojunction device is greater than a potential applied to the silicon first terminal;
the potential applied to the second interface terminal is greater than the threshold voltage of the unipolar device;
a two dimensional carrier gas is formed in substantially all of the active gate region of the heterojunction device; and
a current in the forward conduction mode flows through the two-dimensional carrier gas and the unipolar silicon device.
12. The device of claim 10 , wherein during an on-state reverse conduction mode at least one of:
a potential applied to the second terminal of the heterojunction device is smaller than a potential applied to the silicon first terminal;
the potential applied to the second interface terminal is approximately equal to the potential applied to the silicon first terminal;
a two dimensional carrier gas is formed between at least some of the plurality of pGaN islands; and
a current in a reverse conduction mode flows through the two dimensional carrier gas and a body diode of the unipolar silicon device.
13. The device of claim 10 , wherein during an on-state reverse conduction mode at least one of:
a potential applied to the second terminal of the heterojunction device is less than a potential applied to the silicon first terminal;
the potential applied to the second interface terminal is greater than the potential applied to the silicon first terminal, optionally wherein a difference between the potential applied to the second interface terminal and the potential applied to the silicon first terminal is greater than the threshold voltage of the unipolar device;
a two dimensional carrier gas is formed in substantially all of the active gate region of the heterojunction device; and
a current in a reverse conduction mode flows through the two dimensional carrier gas and the unipolar silicon device or a body diode of the unipolar silicon device.
14. The device according to claim 10 , wherein the heterojunction device is a normally-on device, and wherein the threshold voltage of the heterojunction device is related to at least one of:
(i) the concentration of the highly doped semiconductor regions in the second dimension;
(ii) a charge concentration of the two dimensional carrier gas; and
(iii) a thickness of the III-nitride semiconductor region in the first dimension.
15. The device according to claim 10 , wherein the heterojunction device further comprises a second gate terminal, wherein the second heterojunction gate terminal of the heterojunction device is operatively connected with either (i) a ground or (ii) the first terminal of the unipolar power transistor.
16. The device according to claim 15 , wherein a further at least one of the plurality of pGaN islands is operatively connected to the second heterojunction gate terminal.
17. The device according to claim 1 , further comprising one or more highly doped semiconductor regions between at least two of the plurality of pGaN islands,
wherein the one or more highly doped semiconductor regions have the same conductivity type as the plurality of pGaN islands, and
wherein the one or more highly doped semiconductor regions length in the second dimension is less than a length of the plurality of pGaN islands in the second dimension, and
wherein at least one of the plurality pGaN islands is operatively connected to the heterojunction gate terminal.
18. The device according to claim 1 wherein a gate driver for driving said unipolar power transistor and said heterojunction device is operatively connected to an external control terminal.
19. The device according to claim 18 , wherein the external control terminal is either:
the second interface terminal; or
a terminal of a slew rate control unit.
20. A device comprising:
a heterojunction device comprising a first heterojunction terminal, a second heterojunction terminal and a heterojunction gate terminal operatively connected to an active gate region;
a unipolar power transistor operatively connected in series with said hetero junction device;
an interface unit comprising a first interface terminal and a second interface terminal, wherein a first interface terminal is operatively connected to the heterojunction gate terminal, and
wherein a threshold voltage of said heterojunction device is less than a threshold voltage of said unipolar power transistor and is less than a blocking voltage of said unipolar power transistor,
wherein said heterojunction device is a III-nitride semiconductor based heterojunction device, and wherein said active gate region of the heterojunction device comprises a p-type gallium nitride (pGaN) material,
wherein the active gate region of the heterojunction device comprises a plurality of pGaN islands separated in a third dimension, wherein the threshold voltage of the heterojunction device is related to a size of a separation between adjacent pGaN islands, and wherein the third dimension is perpendicular to the second dimension, and
wherein the heterojunction device and the unipolar power transistor are operable using a single control signal during switching of the device.