Non-conformal capping layer and method forming same

1. A method comprising:

forming a protruding structure; and

forming a non-conformal film on the protruding structure using an Atomic Layer Deposition (ALD) process, wherein the non-conformal film comprises:

a top portion directly over the protruding structure, wherein the top portion has a first thickness; and

a sidewall portion on a sidewall of the protruding structure, wherein the sidewall portion has a second thickness smaller than the first thickness.

2. The method of claim 1 , wherein the ALD process comprises a plasma-assisted ALD process, with plasma being turned on during the ALD process.

3. The method of claim 1 further comprising:

forming a dummy gate electrode layer over the non-conformal film; and

patterning the dummy gate electrode layer.

4. The method of claim 1 , wherein the ALD process comprises a cycle, and the cycle comprises:

conducting a silicon-containing precursor into a reaction chamber;

stopping conducting the silicon-containing precursor;

purging the silicon-containing precursor; and

after the silicon-containing precursor is purged, turning on plasma.

5. The method of claim 4 , wherein the purging is performed using a purging gas, and wherein during a period of time the plasma is turned on, the purging gas is continuously conducted into the reaction chamber.

6. The method of claim 4 , wherein the purging is performed using a purging gas, and wherein during a period of time starting from a first time point the conducting the silicon-containing precursor is ended to a second time point the plasma is turn on, the purging gas is continuously conducted into the reaction chamber.

7. The method of claim 1 , wherein the forming the protruding structure comprises:

forming a protruding semiconductor fin; and

forming a dielectric layer on the protruding semiconductor fin, wherein the non-conformal film is formed on the dielectric layer.

8. The method of claim 7 , wherein the non-conformal film has a bottom end higher than a middle height of the protruding semiconductor fin.

9. An integrated circuit structure comprising:

a semiconductor substrate;

isolation regions extending into the semiconductor substrate;

a semiconductor fin protruding higher than top surfaces of the isolation regions, wherein the isolation regions are on opposing sides of the semiconductor fin;

a dielectric layer on a top surface and sidewalls of the semiconductor fin;

a capping layer comprising a first portion directly over the semiconductor fin, wherein the capping layer comprises:

a top portion overlying the dielectric layer, wherein the top portion has a first thickness; and

a sidewall portion on a sidewall of a top portion of the semiconductor fin, wherein the sidewall portion has a second thickness smaller than the first thickness, and wherein the sidewall portion of the capping layer has a bottom end higher than a middle height of the semiconductor fin;

a gate stack on the semiconductor fin; and

a gate spacer on a sidewall of the gate stack, wherein the gate spacer comprises a portion directly over the capping layer.

10. The integrated circuit structure of claim 9 , wherein a first edge of the top portion of the capping layer physically contacts a second edge of the gate stack.

11. The integrated circuit structure of claim 9 , wherein lower portions of the sidewall portion of the capping layer are thinner than respective upper portions of the sidewall portion of the capping layer.

12. The integrated circuit structure of claim 11 , wherein thicknesses of the sidewall portion of the capping layer continuously increase from the lower portions to the respective upper portions.

13. The integrated circuit structure of claim 9 , wherein the dielectric layer and the capping layer are formed of different materials.

14. The integrated circuit structure of claim 9 , wherein the dielectric layer and the capping layer comprise same elements selected from the group consisting of Si, O, N, and C, and the dielectric layer and the capping layer have different compositions.

15. The integrated circuit structure of claim 9 , wherein the capping layer is free from horizontal portions directly over the isolation regions.

16. The integrated circuit structure of claim 9 further comprising a source/drain region on a side of the gate stack, wherein the capping layer is laterally between the source/drain region and the gate stack.

17. A structure comprising:

a protruding structure protruding higher than features on opposing sides of the protruding structure, wherein the protruding structure comprises a top surface and sidewall surfaces, wherein the protruding structure comprises:

a semiconductor fin; and

a dielectric layer comprising sidewall portions on sidewall surfaces of the semiconductor fin, and a first top portion directly over the top surface of the semiconductor fin;

a dielectric capping layer having a second top portion directly over the first top portion of the dielectric layer, wherein the second top portion of the dielectric capping layer has a uniform thickness, and wherein at least bottom portions of the sidewall surfaces of the protruding structure are free from the dielectric capping layer formed thereon; and

an additional feature in contact with:

the second top portion of the dielectric capping layer; and

lower portions of the sidewall surfaces of the protruding structure.

18. The structure of claim 17 , wherein the protruding structure comprises:

an inner portion; and

a conformal outer portion on the inner portion, wherein a lowest end of the dielectric capping layer is at substantially a same level as the top surface of the inner portion.

19. The structure of claim 18 , wherein the inner portion comprises polysilicon, and the conformal outer portion comprises a dielectric material.

20. The structure of claim 17 , wherein the second top portion of the dielectric capping layer has a thickness in a range between about 5 Å and about 10 Å.