Memory devices and methods of manufacturing thereof
A memory device includes first nanostructures stacked on top of one another; first gate stacks, where two adjacent ones of the first gate stacks wrap around a corresponding first nanostructure; second nanostructures stacked on top of one another; second gate stacks, where two adjacent ones of the second gate stacks wrap around a corresponding second nanostructure; a first drain/source feature electrically coupled to a first end of the first nanostructures; a second drain/source feature electrically coupled to both of a second end of the first nanostructures and a first end of the second nanostructures; and a third drain/source feature electrically coupled to a second end of the second nanostructures. At least one of the plurality of first gate stacks is in direct contact with at least one of the first drain/source feature or the second drain/source feature.
1. A memory device, comprising:
a plurality of first nanostructures stacked on top of one another;
a plurality of first gate stacks, two adjacent ones of the first gate stacks wrapping around a corresponding one of the plurality of first nanostructures, each of the first gate stacks essentially consisting of a first gate metal and a first gate dielectric;
a plurality of second nanostructures stacked on top of one another;
a plurality of second gate stacks, two adjacent ones of the second gate stacks wrapping around a corresponding one of the plurality of second nanostructures, each of the second gate stacks essentially consisting a second gate metal and a second gate dielectric;
a first epitaxially grown feature physically coupled to a first end of each of the first nanostructures;
a second epitaxially grown feature physically coupled to both of a second end of each of the first nanostructures and a first end of each of the second nanostructures; and
a third epitaxially grown feature physically coupled to a second end of each of the second nanostructures,
wherein at least one of the plurality of first gate stacks is in direct contact with at least one of the first epitaxially grown feature or the second epitaxially grown feature, the at least one first gate stack having a whole of its sidewall directly contacting the at least one of the first epitaxially grown feature or the second epitaxially grown feature,
wherein each of the plurality of second gate stacks is electrically isolated from the second epitaxially grown feature by a first dielectric spacer and the first dielectric spacer extends to the first end of each of the second nanostructures.
2. The memory device of claim 1 , wherein each of the plurality of second gate stacks is electrically isolated from the third epitaxially grown feature by a second dielectric spacer.
3. The memory device of claim 1 , wherein each of the plurality of first gate stacks is in direct contact with both of the first epitaxially grown feature and the second epitaxially grown feature.
4. The memory device of claim 1 , wherein the plurality of first gate stacks, the first epitaxially grown feature, and the second epitaxially grown feature are configured as a programming transistor of an anti-fuse memory cell, with the plurality of first nanostructures collectively configured as a conduction channel of the programming transistor, and wherein the plurality of second gate stacks, the second epitaxially grown feature, and the third epitaxially grown feature are configured as a reading transistor of the anti-fuse memory cell, with the plurality of second nanostructures collectively configured as a conduction channel of the reading transistor.
5. The memory device of claim 1 , wherein the plurality of first nanostructures each have a first length extending from the first epitaxially grown feature to the second epitaxially grown feature, and the plurality of first gate stacks each have a second length extending from the first epitaxially grown feature to the second epitaxially grown feature.
6. The memory device of claim 5 , wherein the first length is equal to the second length.
7. The memory device of claim 1 , wherein the plurality of second nanostructures each have a third length extending from the second epitaxially grown feature to the third epitaxially grown feature, and the plurality of second gate stacks each have a fourth length extending from the second epitaxially grown feature to the third epitaxially grown feature.
8. The memory device of claim 7 , wherein the fourth length is less than the third length.
9. The memory device of claim 1 , wherein the plurality of first nanostructures, the plurality of first gate stacks, the first epitaxially grown feature, and the second epitaxially grown feature collectively function as a first transistor of a one-time-programmable (OTP) memory cell, and the plurality of second nanostructures, the plurality of second gate stacks, the second epitaxially grown feature, and the third epitaxially grown feature collectively function as a second transistor of the OTP memory cell.
10. The memory device of claim 9 , wherein the first transistor and second transistor are connected in series through the second epitaxially grown feature.
11. The memory device of claim 9 , wherein the first transistor and second transistor have a same conductive type.
12. The memory device of claim 1 , wherein the plurality of first nanostructures and the plurality of second nanostructures extend along a same horizontal direction.
13. A memory cell, comprising:
a first transistor; and
a second transistor electrically coupled to the first transistor in series by sharing a first epitaxially grown feature,
wherein the first transistor comprises:
a plurality of first nanosheets spaced apart from one another along a vertical direction, the plurality of first nanosheets having a first length along a horizontal direction; and
a plurality of first all-around gate stacks operatively associated with the plurality of first nanosheets, the plurality of first all-around gate stacks having a second length along the horizontal direction, the second length is equal to the first length, each of the first all-around gate stacks essentially consisting of a first gate metal and a first gate dielectric, each of the plurality of first all-around gate stacks having a whole of its sidewall directly contacting the first epitaxially grown feature,
and wherein the second transistor comprises:
a plurality of second nanosheets vertically spaced apart from one another, the plurality of second nanosheets having a third length along the horizontal direction; and
a plurality of second all-around gate stacks operatively associated with the plurality of second nanosheets, the plurality of second all-around gate stacks having a fourth length along the horizontal direction, the fourth length is less than the third length, each of the first all-around gate stacks essentially consisting of a second gate metal and a second gate dielectric;
wherein each of the plurality of second all-around gate stacks is separated from the first epitaxially grown feature with a plurality of inner spacers, each of the plurality of inner spacers having a fifth length along the horizontal direction substantially equal to a difference between the fourth length and third length.
14. The memory cell of claim 13 , further comprising:
a second epitaxially grown feature disposed on a first side of the plurality of first all-around gate stacks, with the first epitaxially grown feature disposed on a second side of the plurality of first all-around gate stacks;
wherein each of the plurality of first all-around gate stacks is in direct contact with both of the first epitaxially grown feature and the second epitaxially grown feature such that the second length is substantially equal to the first length.
15. The memory cell of claim 13 , further comprising:
a third second epitaxially grown feature disposed on a first side of the plurality of second all-around gate stacks, with the first epitaxially grown feature disposed on a second side of the plurality of second all-around gate stacks.
16. The memory cell of claim 13 , wherein the first transistor and second transistor function as a programming transistor and a reading transistor of a one-time-programmable (OTP) memory cell, respectively, and wherein the first transistor and second transistor have a same conductive type.
17. The memory cell of claim 13 , wherein the plurality of inner spacers are partial inner spacers electrically isolating only one end of the plurality of second all-around gate stacks.
18. A memory device, comprising:
a plurality of first nanosheets having a first length along a horizontal direction;
a plurality of first all-around gate stacks operatively associated with the plurality of first nanosheets, the plurality of first all-around gate stacks having a second length along the horizontal direction;
a plurality of second nanosheets having a third length along the horizontal direction; and
a plurality of second all-around gate stacks operatively associated with the plurality of second nanosheets, the plurality of second all-around gate stacks having a fourth length along the horizontal direction;
wherein a first drain/source epitaxially grown feature and a second drain/source epitaxially grown feature are in direct contact with both ends of the plurality of first all-around gate stacks, respectively, such that the second length is equal to the first length, each of the plurality of first all-around gate stacks having a whole of its sidewall directly contacting the first drain/source epitaxially grown feature or the second drain/source epitaxially grown feature; and
wherein the second drain/source epitaxially grown feature and a third drain/source epitaxially grown feature are separated from both ends of the plurality of second all-around gate stacks, respectively, with a plurality of inner spacers, such that the fourth length is less than the third length, wherein the plurality of inner spacers have a fifth length along the horizontal direction substantially equal to a difference in the fourth length and third length.
19. The memory device of claim 18 , wherein the plurality of first nanosheets, the plurality of first all-around gate stacks, the first epitaxially grown feature, and the second epitaxially grown feature collectively function as a first transistor of a one-time-programmable (OTP) memory cell, and the plurality of second nanosheets, the plurality of second all-around gate stacks, the second epitaxially grown feature, and the third epitaxially grown feature collectively function as a second transistor of the OTP memory cell.
20. The memory device of claim 18 , wherein the plurality of inner spacers are partial inner spacers electrically isolating only one end of the plurality of second all-around gate stacks.