Forming stacked nanowire semiconductor device
A semiconductor device comprises a nanowire arranged over a substrate, a gate stack arranged around the nanowire, a spacer arranged along a sidewall of the gate stack, a cavity defined by a distal end of the nanowire and the spacer, and a source/drain region partially disposed in the cavity and in contact with the distal end of the nanowire.
1. A process of forming a semiconductor device obtained by:
forming a nanowire stack comprising a first nanowire and a second nanowire arranged on the first nanowire;
forming a sacrificial gate over the nanowire stack;
forming a sacrificial spacer contacting the sacrificial gate;
removing an exposed portion of the first nanowire to form a first cavity partially defined by the sacrificial spacer, the first nanowire, and the second nanowire;
removing the sacrificial spacer;
depositing a layer of spacer material adjacent to the sacrificial gate and in the first cavity;
removing a portion of the layer of spacer material to form a spacer adjacent to the sacrificial gate and the first nanowire;
removing exposed portions of the second nanowire subsequent to removing the portion of the layer of spacer material to form a spacer adjacent to the sacrificial gate and the first nanowire;
removing a portion of the second nanowire to form a second cavity, the second cavity partially defined by the spacer and the second nanowire; and
epitaxially growing a source/drain region in the second cavity from exposed portions of the second nanowire.
2. The process of claim 1 , wherein the process further comprises:
forming an inter-level dielectric layer over portions of the source/drain region;
removing the sacrificial gate to partially expose a channel region of the second nanowire.
3. The process of claim 2 , wherein the process further comprises removing the first nanowire.
4. The process of claim 3 , wherein the process further comprises, further comprising forming a gate stack over and around the second nanowire.
5. The process of claim 1 , wherein forming the sacrificial spacer comprises:
depositing a layer of spacer material along sidewalls of the sacrificial gate; and
etching to form the sacrificial spacer.
6. The process of claim 1 , wherein removing the exposed portions of the first nanowire includes an anisotropic etching process.
7. The process of claim 1 , wherein removing the exposed portions of the second nanowire includes an anisotropic etching process.
8. The process of claim 1 , wherein removing the portion of the second nanowire to form the second cavity includes an isotropic etching process.
9. The process of claim 1 , wherein the first nanowire includes a first semiconductor material, and the second nanowire includes a second semiconductor material, the first semiconductor material is dissimilar from the second nanowire material.
10. The process of claim 1 , wherein the first nanowire includes a silicon material, and the second nanowire includes a silicon germanium material.
11. A process of forming a semiconductor device obtained by:
forming a semiconductor stack on a substrate, the semiconductor stack comprising a first semiconductor layer and a second semiconductor layer;
removing portions of the semiconductor stack to form a nanowire stack, the nanowire stack comprising a first nanowire and a second nanowire;
forming a sacrificial gate over the nanowire stack;
depositing a first layer of spacer material along sidewalls of the sacrificial gate;
removing portions of the spacer material to form a sacrificial spacer along sidewalls of the sacrificial gate;
removing an exposed portion of the first nanowire to form a first cavity partially defined by the sacrificial spacer, the first nanowire, and the second nanowire;
removing the sacrificial spacer;
depositing a second layer of spacer material contacting the sacrificial gate and in the first cavity;
removing a portion of the second layer of spacer material to form a spacer adjacent to the sacrificial gate and the first nanowire;
removing exposed portions of the second nanowire;
removing a portion of the second nanowire to form a second cavity, the second cavity partially defined by the spacer and the second nanowire; and
epitaxially growing a source/drain region in the second cavity from exposed portions of the second nanowire.
12. The process of claim 11 , wherein the process further comprises:
forming an inter-level dielectric layer over portions of the source/drain region;
removing the sacrificial gate to partially expose a channel region of the second nanowire.
13. The process of claim 11 , wherein the process further comprises:
removing the first nanowire; and
forming a gate stack over and around the first nanowire.