Merging data for write allocate

1. A method, comprising:

receiving, by a level two (L2) controller, a write request for an address that is not allocated as a cache line in a L2 cache, the write request specifying write data;

generating, by the L2 controller, a read request for the address;

reserving, by the L2 controller, an entry in a register file for read data returned in response to the read request;

updating, by the L2 controller, a data field of the entry with the write data;

updating, by the L2 controller, an enable field of the entry associated with the write data; and

receiving, by the L2 controller, the read data and merging the read data into the data field of the entry.

2. The method of claim 1 , further comprising storing the merged data field of the entry as a cache line in the L2 cache.

3. The method of claim 1 , wherein the data field of the entry comprises a plurality of bytes and the enable field of the entry comprises a plurality of sub-fields, each sub-field associated with one of the plurality of bytes.

4. The method of claim 3 , wherein updating the enable field further comprises:

asserting each sub-field associated with a byte containing write data; and

de-asserting each sub-field associated with a byte not containing write data.

5. The method of claim 4 , wherein merging the read data into the data field of the entry further comprises:

discarding the read data associated with an asserted sub-field; and

replacing each byte of the data field associated with a de-asserted sub-field with a corresponding byte of the read data.

6. The method of claim 1 , wherein receiving the read data further comprises:

receiving a first fragment of read data; and

receiving a second fragment of read data;

wherein the method further comprises merging the first and second fragments of read data into the data field of the entry.

7. A level two (L2) cache subsystem, comprising:

a L2 cache;

a register file having an entry; and

a L2 controller configured to:

receive a write request for an address that is not allocated as a cache line in the L2 cache, the write request comprising write data;

generate a read request for the address;

reserve the entry in the register file for read data returned in response to the read request;

update a data field of the entry with the write data;

update an enable field of the entry associated with the write data; and

receive the read data and merge the read data into the data field of the entry.

8. The L2 cache subsystem of claim 7 , wherein the L2 controller is further configured to store the merged data field of the entry as a cache line in the L2 cache.

9. The L2 cache subsystem of claim 7 , wherein the data field of the entry comprises a plurality of bytes and the enable field of the entry comprises a plurality of sub-fields, each sub-field associated with one of the plurality of bytes.

10. The L2 cache subsystem of claim 9 , wherein when the L2 controller updates the enable field, the L2 controller is further configured to:

assert each sub-field associated with a byte containing write data; and

de-assert each sub-field associated with a byte not containing write data.

11. The L2 cache subsystem of claim 10 , wherein when the L2 controller merges the read data into the data field of the entry, the L2 controller is further configured to:

discard the read data associated with an asserted sub-field; and

replace each byte of the data field associated with a de-asserted sub-field with a corresponding byte of the read data.

12. The L2 cache subsystem of claim 7 , wherein when the L2 controller receives the read data, the L2 controller is further configured to:

receive a first fragment of read data;

receive a second fragment of read data; and

merge the first and second fragments of read data into the data field of the entry.

13. An apparatus, comprising:

a central processing unit (CPU) core;

a level one (L1) cache subsystem coupled to the CPU core, the L1 cache subsystem comprising:

a L1 cache; and

a L1 controller; and

a level two (L2) cache subsystem coupled to the L1 cache subsystem, the L2 cache subsystem comprising:

a L2 cache;

a register file having an entry; and

a L2 controller configured to:

receive a write request for an address that is not allocated as a cache line in the L2 cache, the write request comprising write data;

generate a read request for the address;

reserve the entry in the register file for read data returned in response to the read request;

update a data field of the entry with the write data;

update an enable field of the entry associated with the write data; and

receive the read data and merge the read data into the data field of the entry.

14. The apparatus of claim 13 , wherein the L2 controller is further configured to store the merged data field of the entry as a cache line in the L2 cache.

15. The apparatus of claim 13 , wherein the data field of the entry comprises a plurality of bytes and the enable field of the entry comprises a plurality of sub-fields, each sub-field associated with one of the plurality of bytes.

16. The apparatus of claim 15 , wherein when the L2 controller updates the enable field, the L2 controller is further configured to:

assert each sub-field associated with a byte containing write data; and

de-assert each sub-field associated with a byte not containing write data.

17. The apparatus of claim 16 , wherein when the L2 controller merges the read data into the data field of the entry, the L2 controller is further configured to:

discard the read data associated with an asserted sub-field; and

replace each byte of the data field associated with a de-asserted sub-field with a corresponding byte of the read data.

18. The apparatus of claim 13 , wherein when the L2 controller receives the read data, the L2 controller is further configured to:

receive a first fragment of read data;

receive a second fragment of read data; and

merge the first and second fragments of read data into the data field of the entry.