Pipeline arbitration
A method includes receiving, by a first stage in a pipeline, a first transaction from a previous stage in pipeline; in response to first transaction comprising a high priority transaction, processing high priority transaction by sending high priority transaction to a buffer; receiving a second transaction from previous stage; in response to second transaction comprising a low priority transaction, processing low priority transaction by monitoring a full signal from buffer while sending low priority transaction to buffer; in response to full signal asserted and no high priority transaction being available from previous stage, pausing processing of low priority transaction; in response to full signal asserted and a high priority transaction being available from previous stage, stopping processing of low priority transaction and processing high priority transaction; and in response to full signal being de-asserted, processing low priority transaction by sending low priority transaction to buffer.
1 . A circuit, comprising:
a cache subsystem that includes:
a first set of buffers including a first buffer associated with blocking transactions and a second buffer associated with non-blocking transactions;
a second set of buffers;
a multiplexer configured to transmit transactions from the first set of buffers to the second set of buffers; and
an arbitration circuit coupled to the multiplexer and configured to:
determine that a first transaction of the blocking transactions is stored in the first buffer;
attempt to transmit the first transaction from the first buffer to the second set of buffers;
determine whether a second transaction of the non-blocking transactions is stored in the second buffer; and
based on determining that the second transaction is stored in the second buffer,
cause the multiplexer to interrupt the attempted transmission of the first transaction to the second set of buffers; and
cause the multiplexer to transmit the second transaction to the second set of buffers.
2 . The circuit of claim 1 , wherein the first transaction is one of: a blocking read or a blocking write.
3 . The circuit of claim 1 , wherein the second transaction is one of: a non-blocking read, a non-blocking write, or a non-blocking snoop response.
4 . The circuit of claim 1 , wherein the second set of buffers includes at least one of: a buffer associated with the blocking transactions and the non-blocking transactions, a buffer associated with only the blocking transactions, a buffer associated with only the non-blocking transactions, or a buffer associated with only responses to read transactions.
5 . The circuit of claim 1 , wherein:
the second set of buffers is configured to control a full signal; and
the arbitration circuit is configured to:
determine whether the full signal is asserted, in addition to whether the second transaction is stored in the second buffer; and
based on determining that the full signal is asserted and that the second transaction is stored in the second buffer,
cause the multiplexer to interrupt the attempted transmission of the first transaction to the second set of buffers; and
cause the multiplexer to transmit the second transaction to the second set of buffers.
6 . The circuit of claim 5 , wherein the arbitration circuit is configured to:
based on determining that the full signal is asserted and that the second transaction is not stored in the second buffer,
cause the multiplexer to interrupt the attempted transmission of the first transaction to the second set of buffers.
7 . The circuit of claim 5 , wherein the arbitration circuit is configured to:
based on determining that the full signal is not asserted and that the second transaction is not stored in the second buffer,
cause the multiplexer to complete the attempted transmission of the first transaction to the second set of buffers.
8 . The circuit of claim 1 , wherein the second set of buffers includes a third buffer and a fourth buffer, and is configured to provide at least one of: a first full signal indicating that the third buffer is full, or a second full signal indicating that the fourth buffer is full.
9 . The circuit of claim 8 , wherein:
the third buffer is associated with the blocking transactions and the non-blocking transactions, and the fourth buffer is associated with only the non-blocking transactions; and
the arbitration circuit is configured to:
determine whether the first full signal is received indicating that the third buffer is full, in addition to whether the second transaction is stored in the second buffer; and
based on determining that the first full signal is received and that the second transaction is stored in the second buffer,
cause the multiplexer to interrupt the attempted transmission of the first transaction to the second set of buffers; and
cause the multiplexer to transmit the second transaction to the fourth buffer.
10 . The circuit of claim 1 , wherein:
the blocking transactions include blocking transactions of a first priority;
the first set of buffers further includes a third buffer associated with blocking transactions of a second priority, wherein the first priority is lower than the second priority; and
the arbitration circuit is further configured to:
determine whether a third transaction of the blocking transactions of the second priority is stored in the third buffer; and
based on determining that the third transaction is stored in the third buffer,
cause the multiplexer to interrupt the attempted transmission of the first transaction to the second set of buffers; and
cause the multiplexer to transmit the third transaction to the second set of buffers.
11 . The circuit of claim 1 , wherein:
the cache subsystem is a level two (L2) cache subsystem;
the circuit further comprises a level three (L3) cache subsystem; and
the first transaction and the second transaction are transmitted from the L2 cache subsystem to the L3 cache subsystem.
12 . The circuit of claim 1 , wherein:
the cache subsystem is configured to include a set of pipe stages; and
the arbitration circuit is associated with a first subset of the set of pipe stages, not a second subset of the set of pipe stages.
13 . A system, comprising:
a set of transaction requestors configured to provide transactions including blocking transactions and non-blocking transactions; and
a cache subsystem configured to receive the transactions and including:
a first set of buffers including a first buffer configured to store the blocking transactions and a second buffer configured to store the non-blocking transactions;
a second set of buffers;
a multiplexer configured to provide the transactions from the first set of buffers to the second set of buffers; and
an arbitration circuit coupled to the multiplexer and configured to:
determine that a first transaction of the blocking transactions is stored in the first buffer;
attempt to transmit the first transaction from the first buffer to the second set of buffers;
determine whether a second transaction of the non-blocking transactions is stored in the second buffer; and
based on determining that the second transaction is stored in the second buffer,
cause the multiplexer to interrupt the attempted transmission of the first transaction to the second set of buffers; and
cause the multiplexer to transmit the second transaction to the second set of buffers.
14 . The system of claim 13 , wherein the second set of buffers includes at least one of: a buffer associated with the blocking transactions and the non-blocking transactions, a buffer associated with only blocking transactions, a buffer associated with only the non-blocking transactions, or a buffer associated with only responses to read transactions.
15 . The system of claim 13 , wherein:
the blocking transactions include blocking transactions of a first priority;
the first set of buffers further includes a third buffer associated with blocking transactions of a second priority, wherein the first priority is lower than the second priority; and
the arbitration circuit is further configured to:
determine whether a third transaction of the blocking transactions of the second priority is stored in the third buffer; and
based on determining that the third transaction is stored in the third buffer,
cause the multiplexer to interrupt the attempted transmission of the first transaction to the second set of buffers; and
cause the multiplexer to transmit the third transaction to the second set of buffers.
16 . The system of claim 13 , wherein:
the second set of buffers is configured to control a full signal; and
the arbitration circuit is configured to:
determine whether the full signal is asserted, in addition to whether the second transaction is stored in the second buffer;
based on determining that the full signal is asserted and that the second transaction is stored in the second buffer,
cause the multiplexer to interrupt the attempted transmission of the first transaction to the second set of buffers; and
cause the multiplexer to transmit the second transaction to the second set of buffers;
based on determining that the full signal is asserted and that the second transaction is not stored in the second buffer,
cause the multiplexer to interrupt the attempted transmission of the first transaction to the second set of buffers; and
based on determining that the full signal is not asserted and that the second transaction is not stored in the second buffer,
cause the multiplexer to complete the attempted transmission of the first transaction to the second set of buffers.
17 . The system of claim 13 , wherein:
the second set of buffers includes a third buffer associated with the blocking transactions and the non-blocking transactions and a fourth buffer associated with only the non-blocking transactions; and
the arbitration circuit is configured to:
determine whether a full signal is received indicating that the third buffer is full, in addition to whether the second transaction is stored in the second buffer; and
based on determining that the full signal is received and that the second transaction is stored in the second buffer,
cause the multiplexer to interrupt the attempted transmission of the first transaction to the second set of buffers; and
cause the multiplexer to transmit the second transaction to the fourth buffer.
18 . The system of claim 13 , wherein:
the cache subsystem is a level two (L2) cache subsystem;
the system further comprises a level three (L3) cache subsystem; and
the first transaction and the second transaction are transmitted from the L2 cache subsystem to the L3 cache subsystem.
19 . The system of claim 13 , wherein the first transaction is one of: a blocking read or a blocking write.
20 . The system of claim 13 , wherein the second transaction is one of: a non-blocking read, a non-blocking write, or a non-blocking snoop response.