Method of fabricating semiconductor device with metal pad extending into top metal layer

1. A method of fabricating a semiconductor device, comprising:

forming a first metal layer on a substrate;

forming a first dielectric layer on the substrate;

patterning the first dielectric layer, thereby forming a first opening exposing the first metal layer, wherein a first thickness of the first metal layer is removed, and a ratio of the first thickness of the first metal layer to an entire thickness of the first metal layer ranges from ⅕ to ⅓;

forming a second metal layer on the first dielectric layer and filling into the first opening;

patterning the second metal layer, thereby forming a metal pad;

forming a second dielectric layer on the first dielectric layer and the metal pad;

patterning the second dielectric layer, thereby forming a second opening exposing the metal pad; and

performing a first annealing process in an atmosphere of a gas comprising 50 vol % to 100 vol % of hydrogen (H 2 ).

2. The method of fabricating the semiconductor device according to claim 1 , wherein the first annealing process is performed after the patterning the second dielectric layer.

3. The method of fabricating the semiconductor device according to claim 1 , wherein first annealing process is performed in the atmosphere of the gas comprising 100 vol % of hydrogen (H 2 ).

4. The method of fabricating the semiconductor device according to claim 1 , wherein the gas further comprises nitrogen (N 2 ), oxygen (O 2 ), an inert gas, or a combination thereof.

5. The method of fabricating the semiconductor device according to claim 1 , wherein the first annealing process is performed at a temperature between 350° C. and 500° C.

6. The method of fabricating the semiconductor device according to claim 1 , wherein the first annealing process is performed for 20 minutes to 2 hours.

7. The method of fabricating the semiconductor device according to claim 1 , wherein a heating rate of the first annealing process ranges from 40° C./min to 60° C./min.

8. The method of fabricating the semiconductor device according to claim 1 , wherein the forming the first opening comprises:

performing a main etching process; and

performing an over-etching process after performing the main etching process.

9. The method of fabricating the semiconductor device according to claim 8 , wherein a radio frequency (RF) power of the over-etching process is less than 3 times a RF power of the main etching process.

10. The method of fabricating the semiconductor device according to claim 8 , wherein a RF power of the over-etching process is 2 to 3 times a RF power of the main etching process.

11. The method of fabricating the semiconductor device according to claim 1 , further comprising:

performing a second annealing process after forming the first opening.

12. The method of fabricating the semiconductor device according to claim 11 , wherein the second annealing process is performed at a temperature between 400° C. and 800° C., and the second annealing process is performed for 30 minutes to 4 hours.

13. The method of fabricating the semiconductor device according to claim 1 , wherein the first metal layer is a top metal layer.

14. A method of fabricating a semiconductor device, comprising:

forming a first dielectric layer on a first conductive layer;

forming a first opening in the first dielectric layer and the first conductive layer comprising:

performing a main etching process on the first dielectric layer; and

performing an over-etching process to remove a first thickness of the first conductive layer, wherein a ratio of the first thickness of the first conductive layer to an entire thickness of the first conductive layer is greater than ⅕;

forming a second conductive layer on the first dielectric layer and filling into the first opening;

patterning the second conductive layer, thereby forming a conductive pattern on the first dielectric layer and in the first opening,

performing a first annealing process on the first dielectric layer and the first conductive layer having the first opening;

forming a second dielectric layer over the first dielectric layer and the conductive pattern;

forming a second opening in the second dielectric layer, wherein the second opening exposes the conductive pattern; and

performing a second annealing process on the conductive pattern and the second dielectric layer having the second opening,

wherein the first annealing process and the second annealing process are performed in different atmospheres.

15. The method of fabricating the semiconductor device according to claim 14 , wherein a radio frequency (RF) power of the over-etching process is greater than a RF power of the main etching process.

16. The method of fabricating the semiconductor device according to claim 14 , wherein the first annealing process is performed in an oxygen-containing atmosphere, and the second annealing process is performed in a hydrogen-containing atmosphere.

17. The method of fabricating the semiconductor device according to claim 16 , the oxygen-containing atmosphere comprises a H 3 PO 4 /HNO 3 mixture, and the hydrogen-containing atmosphere comprises hydrogen (H 2 ).

18. The method of fabricating the semiconductor device according to claim 14 , further comprising:

forming a third dielectric layer between the first dielectric layer and the first conductive layer, wherein the main etching process is performed by using the third dielectric layer as an etching stop layer.

19. A method of fabricating a semiconductor device, comprising:

forming a first passivation layer on a top metal layer of an interconnect structure;

patterning the first passivation layer comprising:

performing a main etching process to form the first opening in the first passivation layer; and

performing an over-etching process to form a recess in the top metal layer;

performing a first annealing process on the first passivation layer having the first opening and the top metal layer having the recess;

forming a barrier layer on a top surface of the first passivation layer and filling into the first opening in the first passivation layer and the recess in the top metal layer;

forming a conductive layer on the barrier layer in the first opening and the recess;

patterning the conductive layer, thereby forming a conductive pad on a first portion of the top surface of the first passivation layer and in the first opening and the recess, wherein a second portion of the top surface of the first passivation layer is exposed;

forming a second passivation layer over the first passivation layer and the conductive pad; and

patterning the second passivation layer to form a second opening, wherein the second opening exposes the conductive pad; and

performing a second annealing process on the conductive pad and the second passivation layer having the second opening,

wherein the first annealing process and the second annealing process are performed in different atmospheres.

20. The method of fabricating the semiconductor device according to claim 19 , wherein the first annealing process is performed in an oxygen-containing atmosphere, and the second annealing process is performed in a hydrogen-containing atmosphere.