Hybrid interconnect structure for self aligned via

1. An interconnect structure, comprising:

a first metal line comprising a first conductive material disposed within a first dielectric layer over a substrate and a second conductive material disposed within the first dielectric layer and directly over a top of the first conductive material, wherein the second conductive material is different from the first conductive material;

a second dielectric layer disposed over the first dielectric layer;

a first via comprising a third conductive material disposed within the second dielectric layer and on a top of the second conductive material; and

a second metal line comprising a fourth conductive material disposed within the second dielectric layer over the first via,

wherein the second conductive material and the third conductive material have lower diffusion coefficients than the first conductive material and the fourth conductive material.

2. The interconnect structure of claim 1 ,

wherein sidewalls of the second third metal line are laterally separated from sidewalls of the second dielectric layer by a barrier layer.

3. The interconnect structure of claim 1 , wherein sidewalls of the first via are in contact with sidewalls of the second dielectric layer.

4. The interconnect structure of claim 1 , wherein a bottommost surface of the second conductive material is over a top surface of the first conductive material.

5. The interconnect structure of claim 1 , wherein the second conductive material completely covers a top surface of the first conductive material.

6. The interconnect structure of claim 1 , further comprising:

a barrier layer separating both the first via and the second metal line from the second dielectric layer.

7. The interconnect structure of claim 1 , wherein the second conductive material directly contacts the top of the first conductive material along an interface that is below a top of the first dielectric layer.

8. The interconnect structure of claim 1 , wherein the first via is vertically separated from the first conductive material by the second conductive material.

9. The interconnect structure of claim 1 ,

wherein the first conductive material comprises copper or cobalt; and

wherein the second conductive material and the third conductive material comprise a refractory metal.

10. An interconnect structure, comprising:

a first metal line comprising a first metal and a second metal over a topmost surface of the first metal, wherein the second metal is different from the first metal;

a first dielectric layer laterally surrounding the first metal line;

a first via comprising the second metal over the first metal line;

a second metal line comprising the first metal over the first via; and

a second dielectric layer laterally surrounding the first via and the second metal line, wherein the second dielectric layer is vertically separated from the first dielectric layer by an etch stop layer.

11. The interconnect structure of claim 10 , wherein the first metal line is electrically connected to the second metal line through the first via.

12. The interconnect structure of claim 11 , wherein the second metal has a higher resistivity to diffusion than the first metal.

13. The interconnect structure of claim 10 , further comprising:

a barrier layer laterally surrounding the first via and the second metal line, wherein the barrier layer laterally separates the first via and the second metal line from the second dielectric layer.

14. An integrated chip, comprising:

a first dielectric layer over a substrate;

a first metal line within the first dielectric layer, the first metal line comprising a first metal and a second metal different from the first metal;

a second metal line within the first dielectric layer and laterally spaced apart from the first metal line by the first dielectric layer, the second metal line comprising the first metal and the second metal;

a metal via directly over and on the first metal line, the metal via comprising the second metal; and

a third metal line directly over the metal via, the third metal line comprising a metal different from the second metal,

wherein the second metal of the first metal line is on a top surface of the first metal of the first metal line, and wherein the second metal of the second metal line is on a top surface of the first metal of the second metal line.

15. The integrated chip of claim 14 , wherein a bottom of the first metal is disposed at a first height, wherein a top of the second metal is disposed at a second height, and wherein the first dielectric layer continuously extends from the first height to the second height.

16. The integrated chip of claim 14 , wherein the first metal of the first metal line abuts the second metal of the first metal line at an interface that is below a top surface of the first dielectric layer and that is above a bottom surface of the first dielectric layer.

17. The integrated chip of claim 14 , wherein the first metal of the first metal line is laterally separated from the first metal of the second metal line by the first dielectric layer, and wherein the second metal of the first metal line is laterally separated from the second metal of the second metal line by the first dielectric layer.

18. The integrated chip of claim 14 , wherein the first metal line is laterally separated from the second metal line by a first distance, wherein a second distance exists between a sidewall of the metal via and the sidewall of the second metal line, and wherein the second distance is smaller than the first distance.

19. The integrated chip of claim 14 , further comprising:

a barrier layer lining the metal via and the third metal line, wherein the third metal line is on a top surface of the metal via.

20. The integrated chip of claim 14 , further comprising:

a barrier layer lining the third metal line and extending between the metal via and the third metal line.