IP Library Granted Patent US 11,635,566
Granted Patent B2
US 11,635,566 · App. 16/884,843 · Granted Apr 25, 2023

Package and method of forming same

Inventors: Chih-Hsuan Tai (Taipei, TW); Chung-Ming Weng (Hsinchu, TW); Hung-Yi Kuo (Taipei, TW); Cheng-Chieh Hsieh (Tainan, TW); Hao-Yi Tsai (Hsinchu, TW); Chung-Shi Liu (Hsinchu, TW); Chen-Hua Yu (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
G02B6/12004G02B6/13G02B6/4249G02B6/43H01L23/49827H01L23/49838G02B2006/12147
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Quick Facts
Patent No.
US 11,635,566
App. No.
16/884,843
Granted
Apr 25, 2023
Kind
B2
Abstract

An integrated circuit package and a method of forming the same are provided. The integrated circuit package includes a photonic integrated circuit die. The photonic integrated circuit die includes an optical coupler. The integrated circuit package further includes an encapsulant encapsulating the photonic integrated circuit die, a first redistribution structure over the photonic integrated circuit die and the encapsulant, and an opening extending through the first redistribution structure and exposing the optical coupler.

Claims (34)

1. An integrated circuit package comprising:

a photonic integrated circuit die, the photonic integrated circuit die comprising an optical coupler and a die connector adjacent to the optical coupler;

an encapsulant encapsulating the photonic integrated circuit die;

a first redistribution structure over the photonic integrated circuit die and the encapsulant, the first redistribution structure comprising a metallization pattern in physical contact with the die connector; and

an opening exposing the optical coupler and a sidewall of the first redistribution-structure, wherein the opening extends into the photonic integrated circuit die.

2. The integrated circuit package of claim 1 , wherein the optical coupler is an edge coupler.

3. The integrated circuit package of claim 1 , further comprising an optical fiber coupled to the optical coupler.

4. The integrated circuit package of claim 1 , further comprising a second redistribution structure below the photonic integrated circuit die and the encapsulant.

5. The integrated circuit package of claim 4 , further comprising a through via within the encapsulant and electrically coupling the first redistribution structure to the second redistribution structure.

6. The integrated circuit package of claim 1 , further comprising a package substrate attached to the first redistribution structure.

7. An integrated circuit package comprising:

an encapsulant having a first surface and a second surface opposite the first surface;

a photonic integrated circuit die embedded in the encapsulant, the photonic integrated circuit die comprising an optical coupler, a first surface of the photonic integrated circuit die being level with the first surface of the encapsulant;

a first redistribution structure on the first surface of the encapsulant, the first redistribution structure comprising a first metallization pattern;

a second redistribution structure on the second surface of the encapsulant, the second redistribution structure comprising a second metallization pattern electrically coupled to the first metallization pattern; and

an opening exposing the optical coupler, a sidewall of the opening extending through the first redistribution structure, wherein the opening extends into an interconnect structure of the photonic integrated circuit die.

8. The integrated circuit package of claim 7 , wherein the optical coupler is an edge coupler.

9. The integrated circuit package of claim 7 , wherein a portion of the opening extends from the first surface of the photonic integrated circuit die toward a second surface of the photonic integrated circuit die, and wherein the second surface of the photonic integrated circuit die is opposite the first surface of the photonic integrated circuit die.

10. The integrated circuit package of claim 7 , wherein a first sidewall of the photonic integrated circuit die proximate to the optical coupler is free from the encapsulant.

11. The integrated circuit package of claim 10 , wherein a second sidewall of the photonic integrated circuit die is in physical contact with the encapsulant, and wherein the second sidewall of the photonic integrated circuit die is opposite the first sidewall of the photonic integrated circuit die.

12. The integrated circuit package of claim 7 , further comprising a through via within the encapsulant, the through via extending from the first surface of the encapsulant to the second surface of the encapsulant.

13. The integrated circuit package of claim 7 , further comprising an optical fiber extending into the opening and coupled to the optical coupler.

14. An integrated circuit package comprising:

a first redistribution structure comprising a first metallization pattern;

a photonic integrated circuit die over the first redistribution structure, a backside of the photonic integrated circuit die being attached to the first redistribution structure, a front side of the photonic integrated circuit die comprising an optical coupler adjacent to a first sidewall of the photonic integrated circuit die;

an encapsulant over the first redistribution structure, the encapsulant extending along and being in physical contact with a second sidewall of the photonic integrated circuit die, the first sidewall of the photonic integrated circuit die being free from the encapsulant, the second sidewall of the photonic integrated circuit die being opposite to the first sidewall of the photonic integrated circuit die;

a second redistribution structure over and in electrical contact with the photonic integrated circuit die, the second redistribution structure comprising a second metallization pattern electrically coupled to the first metallization pattern; and

an opening extending into photonic integrated circuit die and exposing the optical coupler.

15. The integrated circuit package of claim 14 , wherein the optical coupler is an edge coupler.

16. The integrated circuit package of claim 14 , wherein a sidewall of the second redistribution structure proximate to the first sidewall of the photonic integrated circuit die is a sloped sidewall.

17. The integrated circuit package of claim 14 , wherein the backside of the photonic integrated circuit die is attached to the first redistribution structure using an adhesive layer.

18. The integrated circuit package of claim 14 , wherein a bottom of the opening is below a top surface of the encapsulant.

19. The integrated circuit package of claim 14 , further comprising an optical fiber coupled to the optical coupler.

20. The integrated circuit package of claim 1 , wherein a top surface of the die connector is above a bottom of the opening.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: TAI, CHIH-HSUAN; WENG, CHUNG-MING; KUO, HUNG-YI; HSIEH, CHENG-CHIEH; TSAI, HAO-YI; LIU, CHUNG-SHI; YU, CHEN-HUA
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 052764/0838 →
Continuity (2)
Provisional Application 62941229 · Nov 27, 2019
Related Publication 20210157052A1 · May 27, 2021
Cited By (2)
US 12,546,937 US 12,616,017