ELECTROSTATIC DISCHARGE (ESD) ROBUST TRANSISTORS AND RELATED METHODS
An electrostatic discharge robust semiconductor transistor (transistor) includes a semiconductor substrate of a first conductivity type, a substrate contact region of the first conductivity type coupled with the semiconductor substrate, a source region of a second conductivity type, a channel region of the second conductivity type, a gate region of the first conductivity type, a drain region having a first drain region of the first conductivity type and a second drain region of the second conductivity type, and an electrical conductor coupled over the second drain region and a portion of the first drain region. A portion of the first drain region not covered by the electrical conductor forms a resistive electrical ballast region configured to protect the transistor from electrostatic discharge (ESD) induced voltage pulses. In implementations the transistor includes a silicon controlled rectifier (SCR) junction field effect transistor (SCR JFET) or a laterally diffused metal-oxide semiconductor (SCR LDMOS).
1 . An electrostatic discharge robust semiconductor transistor, comprising:
a semiconductor substrate of a first conductivity type;
a substrate contact region and a gate region of the first conductivity type and a source region and a channel region of a second conductivity type all operatively coupled with the semiconductor substrate;
a drain region comprising a first drain region of the first conductivity type and a second drain region of the second conductivity type, the drain region coupled with the semiconductor substrate; and
an electrical conductor coupled over only a first portion of the first drain region;
wherein a second portion of the first drain region becomes a resistive electrical ballast region configured to protect the transistor from electrostatic discharge (ESD) induced voltage pulses.
2 . The transistor of claim 1 , wherein the first conductivity type is P type conductivity, the second conductivity type is N type conductivity and the channel region comprises an N− channel region.
3 . The transistor of claim 2 , wherein the semiconductor substrate comprises a P type substrate, the substrate contact region comprises a P+ substrate contact region, the source region comprises an N+ source region, the gate region comprises a P+ gate region, the first drain region comprises a P+ drain region, and the second drain region comprises an N+ drain region.
4 . The transistor of claim 1 , wherein the electrical conductor comprises a silicide.
5 . The transistor of claim 1 , wherein the resistive electrical ballast region comprises a width of at least 3 microns.
6 . The transistor of claim 1 , wherein the resistive electrical ballast region comprises a separation layer between the electrical conductor and an electrically insulative region. The transistor of claim 1 , wherein the transistor comprises a stadium shape.
8 . An electrostatic discharge robust semiconductor transistor, comprising:
a semiconductor substrate of a first conductivity type;
a first substrate contact region of the first conductivity type coupled with the semiconductor substrate;
a source region of a second conductivity type coupled with the semiconductor substrate;
a channel region of the second conductivity type;
a gate region of the first conductivity type;
a drain region comprising a first drain region of the first conductivity type and a second drain region of the second conductivity type, the drain region coupled with the semiconductor substrate;
a second substrate contact region of the second conductivity type coupled with the semiconductor substrate; and
an electrical conductor coupled over only a first portion of the first drain region;
wherein a second portion of the first drain region becomes a resistive electrical ballast region configured to protect the transistor from electrostatic discharge (ESD) induced voltage pulses.
9 . The transistor of claim 8 , wherein the first conductivity type is P type conductivity and the second conductivity type is N type conductivity and wherein the channel region comprises an N− channel region.
10 . The transistor of claim 8 , wherein the semiconductor substrate comprises a P type substrate, the first substrate contact region comprises a P+ substrate contact region, the source region comprises an N+ source region, the channel region comprises an N− channel region, the gate region comprises a P+ gate region, the first drain region comprises a P+ drain region (P+ anode), the second drain region comprises an N+ drain region, and the second substrate contact region comprises an N+ substrate contact region (N+ cathode).
11 . The transistor of claim 8 , wherein the electrical conductor comprises a silicide.
12 . The transistor of claim 8 , wherein the resistive electrical ballast region comprises a width of at least 3 microns.
13 . The transistor of claim 8 , wherein the resistive electrical ballast region comprises a separation layer between the electrical conductor and an electrically insulative region.
14 . The transistor of claim 8 , wherein the transistor comprises a stadium shape.
15 . An electrostatic discharge robust semiconductor transistor, comprising:
a semiconductor substrate of a first conductivity type;
a substrate contact region, a first well region, and a gate region of the first conductivity type and a source region and a second well region of a second conductivity type all operatively coupled with the semiconductor substrate;
a drain region comprising a first drain region of the first conductivity type and a second drain region of the second conductivity type, the drain region coupled with the semiconductor substrate; and
a silicide coupled over only a first portion of the first drain region;
wherein a second portion of the first drain region becomes a resistive electrical ballast region configured to protect the transistor from electrostatic discharge (ESD) induced voltage pulses.
16 . The transistor of claim 15 , wherein the first conductivity type is P type conductivity and the second conductivity type is N type conductivity.
17 . The transistor of claim 16 , wherein the semiconductor substrate comprises a P type substrate, the substrate contact region comprises a P+ substrate contact region, the first well region comprises a P well region, the second well region comprises an N well region, the source region comprises an N+ source region, the gate region comprises an N+ gate region, the first drain region comprises a P+ drain region, and the second drain region comprises an N+ drain region.
18 . The transistor of claim 15 , wherein the first well region fully separates the substrate contact region from the semiconductor substrate and the first well region directly contacts the semiconductor substrate.
19 . The transistor of claim 15 , wherein the second well region fully separates the first well region from the semiconductor substrate.
20 . The transistor of claim 15 , wherein the resistive electrical ballast region comprises a width of at least 3 microns.