Semiconductor devices with backside air gap dielectric

1. A method, comprising:

providing a structure having transistors, an isolation structure that is at least partially over the transistors, two metal plugs through the isolation structure and electrically connecting to electrodes of the transistors, and a trench, wherein the isolation structure and the two metal plugs form sidewalls of the trench;

forming a dielectric liner on the sidewalls of the trench and over the isolation structure and the metal plugs, wherein the dielectric liner is thicker at an opening portion of the trench than at another portion of the trench that is deeper than the opening portion so that an air gap is formed inside the trench and the air gap is fully or partially surrounded by the dielectric liner;

depositing a sacrificial dielectric layer over the dielectric liner and over the air gap; and

performing a chemical-mechanical planarization (CMP) process to remove the sacrificial dielectric layer and to recess the dielectric liner until the isolation structure and the metal plugs are exposed, wherein the air gap remains inside the trench.

2. The method of claim 1 , further comprising:

forming a dielectric layer over the isolation structure, the dielectric liner, the air gap, and the metal plugs, wherein the air gap is sealed by the dielectric liner alone or by both the dielectric liner and the dielectric layer; and

forming conductors in the dielectric layer, wherein the conductors are electrically connected to the metal plugs.

3. The method of claim 1 , wherein the forming of the dielectric liner includes using plasma enhanced chemical vapor deposition (PECVD).

4. The method of claim 3 , wherein the PECVD includes applying plasma generated from SiH 4 gas and N 2 or NH 3 gas.

5. The method of claim 1 , before the forming of the dielectric liner, further comprising:

treating the sidewalls of the trench with a plasma having atoms of nitrogen, fluorine, chlorine, oxygen, hydrogen, or argon.

6. The method of claim 1 , wherein the providing of the structure includes:

receiving a workpiece having a substrate with active regions, wherein the isolation structure isolates the active regions, and the transistors are formed over the active regions, the workpiece further having an interconnect structure over the transistors, wherein the substrate is at a backside of the workpiece and the interconnect structure is at a frontside of the workpiece;

attaching the frontside of the workpiece to a carrier wafer;

thinning the workpiece from the backside of the workpiece until the isolation structure and the active regions are exposed from the backside of the workpiece;

etching two holes through the active regions to expose the electrodes of the transistors from the backside of the workpiece;

forming the two metal plugs in the two holes respectively; and

etching the active regions between the two metal plugs from the backside of the workpiece, thereby forming the trench.

7. The method of claim 6 , wherein the transistors include FinFETs and the active regions include semiconductor fins.

8. The method of claim 6 , wherein the transistors include gate-all-around FETs and the active regions include semiconductor fins.

9. The method of claim 1 , wherein the trench is as deep as or deeper than the metal plugs.

10. A method, comprising:

providing a structure having a silicon substrate, an isolation structure over the silicon substrate, one or more semiconductor fins extending from the silicon substrate and over the isolation structure, one or more transistors formed over the one or more semiconductor fins, and an interconnect structure over the one or more transistors, wherein the silicon substrate is at a backside of the structure and the interconnect structure is at a frontside of the structure;

attaching the frontside of the structure to a carrier substrate;

thinning the structure from the backside of the structure until the isolation structure and the one or more semiconductor fins are exposed from the backside of the structure;

etching two holes through the one or more semiconductor fins to expose two source/drain features of the one or more transistors from the backside of the structure;

forming two metal plugs in the two holes respectively;

etching the one or more semiconductor fins between the two metal plugs from the backside of the structure, thereby forming a trench; and

forming a dielectric liner on sidewalls of the trench and over the isolation structure and the metal plugs, wherein the dielectric liner is thicker at an opening portion of the trench than at another portion of the trench that is deeper than the opening portion so that an air gap is formed inside the trench.

11. The method of claim 10 , wherein the trench is as deep as or deeper than the metal plugs from the backside of the structure.

12. The method of claim 10 , wherein the air gap is fully surrounded by the dielectric liner alone.

13. The method of claim 10 , further comprising:

depositing a sacrificial dielectric layer over the dielectric liner and over the air gap; and

performing a chemical-mechanical planarization (CMP) process to remove the sacrificial dielectric layer and to recess the dielectric liner until the isolation structure and the metal plugs are exposed, wherein the air gap remains inside the trench.

14. The method of claim 13 , after the performing of the CMP process, further comprising:

forming another interconnect structure over the backside of the structure and over the dielectric liner, the air gap, and the metal plugs.

15. The method of claim 10 , wherein the forming of the dielectric liner includes using plasma enhanced chemical vapor deposition (PECVD) with plasma generated from SiH 4 gas and NH 3 gas.

16. A method, comprising:

providing a structure having a substrate, an isolation structure over the substrate, one or more semiconductor fins extending from the substrate and above the isolation structure, one or more transistors formed over the one or more semiconductor fins, wherein the substrate is at a backside of the structure and the one or more transistors are at a frontside of the structure;

thinning the structure from the backside of the structure until the isolation structure and the one or more semiconductor fins are exposed from the backside of the structure;

etching two holes through the one or more semiconductor fins to expose two source/drain features of the one or more transistors from the backside of the structure;

forming two metal plugs in the two holes respectively;

selectively etching the one or more semiconductor fins between the two metal plugs from the backside of the structure, thereby forming a trench;

forming a dielectric liner on sidewalls of the trench and over the isolation structure and the metal plugs, wherein the dielectric liner is thicker at an opening portion of the trench than at another portion of the trench that is deeper than the opening portion;

depositing a sacrificial dielectric layer covering the dielectric liner; and

performing a chemical-mechanical planarization (CMP) process to remove the sacrificial dielectric layer and to recess the dielectric liner until the isolation structure and the metal plugs are exposed.

17. The method of claim 16 , wherein the forming of the dielectric liner also forms an air gap inside the trench, and the sacrificial dielectric layer is deposited to cover the air gap without completely filling the air gap.

18. The method of claim 17 , after performing the CMP process, further comprising:

forming a second dielectric layer on the backside of the structure, wherein the air gap is sealed by the dielectric liner alone or by both the dielectric liner and the second dielectric layer.

19. The method of claim 16 , wherein the trench is deeper than the metal plugs from the backside of the structure.

20. The method of claim 16 , wherein the forming of the dielectric liner includes using plasma enhanced chemical vapor deposition (PECVD) that applies plasma generated from SiH 4 gas and N 2 or NH 3 gas.