Integrated substrate and manufacturing method thereof
View Patent ↗An integrated substrate for testing a semiconductor wafer and a method are provided. The integrated substrate includes a first redistribution structure including a fine redistribution circuitry, a plurality of testing tips disposed on a first surface of the first redistribution structure and electrically connected to the fine redistribution circuitry to probe the semiconductor wafer, a second redistribution structure including a coarse redistribution circuitry and disposed over a second surface of the first redistribution structure opposite to the first surface, and a plurality of conductive joints interposed between the coarse redistribution circuitry and the fine redistribution circuitry to provide electrical connections therebetween. A layout density of the fine redistribution circuitry is denser than that of the coarse redistribution circuitry.
1. An integrated substrate for testing a semiconductor wafer, comprising:
a first redistribution structure comprising a fine redistribution circuitry;
a plurality of testing tips disposed on a first surface of the first redistribution structure and electrically connected to the fine redistribution circuitry to probe the semiconductor wafer;
a second redistribution structure comprising a coarse redistribution circuitry and disposed over a second surface of the first redistribution structure opposite to the first surface of the first redistribution structure, wherein a layout density of the fine redistribution circuitry is denser than that of the coarse redistribution circuitry, and wherein a first surface of the second redistribution structure facing towards the second surface of the first redistribution structure;
a plurality of conductive joints interposed between the coarse redistribution circuitry of the second redistribution structure and the fine redistribution circuitry of the first redistribution structure to provide electrical connections therebetween; and
an underfill layer interposed between the second surface of the first redistribution structure and the first surface of the second redistribution structure to laterally cover the plurality of conductive joints,
wherein the coarse redistribution circuitry of the second redistribution structure has coarse conductive patterns, each of the coarse conductive patterns is in contact with one of the conductive joints with a contact surface, and
the contact surface is closer to the second surface of the first redistribution structure than the first surface of the second redistribution structure, and the contact surface is laterally covered by the underfill layer.
2. The integrated substrate according to claim 1 , further comprising:
a plurality of conductive terminals disposed on and electrically connected to the coarse redistribution circuitry of the second redistribution structure and located opposite to the plurality of conductive joints.
3. The integrated substrate according to claim 2 , wherein the plurality of conductive joints are solder joints, and the plurality of conductive terminals are solder terminals.
4. The integrated substrate according to claim 1 , wherein the first redistribution structure further comprises a fine dielectric layer covering the fine redistribution circuitry.
5. The integrated substrate according to claim 1 , wherein a coarse dielectric layer of the second redistribution structure that covers the coarse redistribution circuitry is thicker and more rigid than a fine dielectric layer of the first redistribution structure that covers the fine redistribution circuitry.
6. The integrated substrate according to claim 1 , wherein a pitch of adjacent two of the plurality of testing tips matches a fine-pitch requirement of testing pads of the semiconductor wafer to be tested, and the plurality of testing tips are arranged to be in direct contact with the semiconductor wafer to be tested.