IP Library › Granted Patent US 11,404,436
Granted Patent B2
US 11,404,436 · App. 16/891,297 · Granted Aug 2, 2022

Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells

Inventors: Jordan D. Greenlee (Boise, ID); John D. Hopkins (Meridian, ID)
Assignee: Micron Technology, Inc.
H01L27/11582H01L21/32155H01L27/1157H01L27/11519H01L27/11524H01L27/11556H01L27/11565
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Quick Facts
Patent No.
US 11,404,436
App. No.
16/891,297
Granted
Aug 2, 2022
Kind
B2
Abstract

A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions are formed and individually comprise a vertical stack comprising alternating first tiers and second tiers directly above the conductor tier. Channel-material strings of memory cells extend through the first tiers and the second tiers. Horizontally-elongated lines are formed in the conductor material between the laterally-spaced memory-block regions. The horizontally-elongated lines are of different composition from an upper portion of the conductor material that is laterally-between the horizontally-elongated lines. After the horizontally-elongated lines are formed, conductive material of a lowest of the first tiers is formed that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. Other embodiments, including structure independent of method, are disclosed.

Claims (20)

1. A method used in forming a memory array comprising strings of memory cells, comprising:

forming a conductor tier comprising conductor material on a substrate;

forming laterally-spaced memory-block regions individually comprising a vertical stack comprising alternating first tiers and second tiers directly above the conductor tier, channel-material strings of memory cells extending through the first tiers and the second tiers;

forming horizontally-elongated lines in the conductor material between the laterally-spaced memory-block regions, the horizontally-elongated lines being of different composition from an upper portion of the conductor material that is laterally-between the horizontally-elongated lines; and

after forming the horizontally-elongated lines, forming conductive material in a lowest of the first tiers that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier.

2. The method of claim 1 comprising forming the horizontally-elongated lines before forming the vertical stack.

3. The method of claim 1 comprising forming the horizontally-elongated lines after forming the vertical stack.

4. The method of claim 1 wherein the horizontally-elongated lines extend laterally into areas of the memory-block regions that are there-above.

5. The method of claim 1 wherein the horizontally-elongated lines are not as vertically thick as the conductor tier.

6. The method of claim 1 wherein the horizontally-elongated lines have greater content of one or more of C, N, B, As, Sb, Bi, Li, Al, In, or a metal material than is present in the conductor material that is laterally-between the horizontally-elongated lines.

7. The method of claim 1 wherein the horizontally-elongated lines are not conductive.

8. The method of claim 1 wherein the horizontally-elongated lines are conductive.

9. The method of claim 1 wherein the horizontally-elongated lines are formed by ion implanting into the conductor material through mask openings in a masking material.

10. The method of claim 1 wherein a lowest surface of the channel material of the channel-material-strings is never directly against any of the conductor material of the conductor tier.

11. A method used in forming a memory array comprising strings of memory cells, comprising:

forming a conductor tier comprising conductor material on a substrate;

forming horizontally-elongated lines in the conductor material between what will comprise laterally-spaced memory-block regions there-above, the horizontally-elongated lines being of different composition from an upper portion of the conductor material that is laterally-between the horizontally-elongated lines;

after forming the horizontally-elongated lines, forming a stack comprising vertically-alternating first tiers and second tiers above the conductor tier, a lowest of the first tiers comprising sacrificial material of different composition from that of an uppermost portion of the horizontally-elongated lines in the conductor material, the stack comprising the laterally-spaced memory-block regions having horizontally-elongated trenches there-between that are individually directly above individual of the horizontally-elongated lines in the conductor material in the conductor tier, channel-material strings extending through the first tiers and the second tiers, material of the first tiers being of different composition from material of the second tiers;

isotropically etching the sacrificial material from the lowest first tier; and

after the isotropically etching, forming conductive material in the lowest first tier that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 16, 2024
From: MICRON TECHNOLOGY, INC.
To: LODESTAR LICENSING GROUP LLC
Reel/Frame 066131/0860 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 3, 2020
From: GREENLEE, JORDAN D.; HOPKINS, JOHN D.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 052821/0796 →
Continuity (1)
Related Publication 20210384216A1 · Dec 9, 2021
Cited By (1)
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