Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells
View Patent ↗A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions are formed that individually comprise a vertical stack comprising alternating first tiers and second tiers directly above the conductor tier. Channel-material strings of memory cells extend through the first tiers and the second tiers. Horizontally-elongated lines are formed in the conductor tier between the laterally-spaced memory-block regions. The horizontally-elongated lines are of different composition from an upper portion of the conductor material and comprise metal material. After the horizontally-elongated lines are formed, conductive material is formed in a lower of the first tiers and that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. Other embodiments, including structure independent of method, are disclosed.
1. A memory array comprising strings of memory cells, comprising:
a conductor tier comprising conductor material;
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above the conductor tier, channel-material strings of memory cells extending through the insulative tiers and the conductive tiers, conducting material of a lower of the conductive tiers directly electrically coupling together the channel material of individual of the channel-material strings and the conductor material of the conductor tier;
intervening material laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks, the intervening material comprising insulating material; and
horizontally-elongated lines in an upper portion of the conductor tier between the laterally-spaced memory blocks, the horizontally-elongated lines being of different composition from an upper portion of the conductor material and comprising metal material.
2. The memory array of claim 1 wherein the horizontally-elongated lines extend laterally into areas of the memory blocks that are there-above.
3. The memory array of claim 1 wherein the horizontally-elongated lines are not as vertically thick as the conductor tier.
4. The memory array of claim 1 wherein the horizontally-elongated lines are conductive.
5. The memory array of claim 1 wherein the horizontally-elongated lines comprise an elemental-form metal.
6. The memory array of claim 1 wherein the horizontally-elongated lines comprise a metal silicide.
7. A memory array comprising strings of memory cells, comprising:
a conductor tier comprising conductively-doped polysilicon;
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above the conductor tier, channel-material strings of memory cells extending through the insulative tiers and the conductive tiers, a lowest of the conductive tiers comprising conductively-doped polysilicon directly against the conductively-doped polysilicon of the conductor tier and directly against a sidewall of channel material of the channel-material strings in the lowest conductive tier;
intervening material laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks, the intervening material comprising insulating material; and
horizontally-elongated lines in an upper portion of the conductor tier between the laterally-spaced memory blocks, the horizontally-elongated lines comprising at least one of a metal silicide or elemental-form metal.
8. The memory array of claim 7 wherein the horizontally-elongated lines extend laterally into areas of the memory blocks that are there-above.
9. The memory array of claim 7 wherein the horizontally-elongated lines are not as vertically thick as the conductor tier.
10. The memory array of claim 7 wherein the horizontally-elongated lines are conductive.
11. The memory array of claim 7 wherein the horizontally-elongated lines comprise the elemental-form metal.
12. The memory array of claim 7 wherein the horizontally-elongated lines comprise the metal silicide.