Memory with symmetric read current profile and read method thereof

1. A memory, comprising:

a first memory array configured to store main data;

a second memory array configured to store complement data that is complementary to the main data; and

a read circuit, comprising:

a first sense amplifier configured to provide a first sensing signal according to a reference signal and first data of the main data corresponding to a first address signal;

a second sense amplifier configured to provide a second sensing signal according to the reference signal and second data of the complement data corresponding to the first address signal; and

an output buffer configured to provide one of the first sensing signal and the second sensing signal as an output according to a control signal.

2. The memory as claimed in claim 1 , wherein the first sense amplifier is coupled between the first memory array and the output buffer, and the second sense amplifier is coupled between the second memory array and the output buffer.

3. The memory as claimed in claim 1 , wherein the output buffer comprises:

a first selector coupled to the first sense amplifier and the second sense amplifier, and configured to selectively provide the first sensing signal or the second sensing signal as the output according to the control signal.

4. The memory as claimed in claim 1 , further comprising:

a first decoder coupled between the first memory array and the first sense amplifier, and configured to selectively provide a signal of the first data to the first sense amplifier according to the first address signal; and

a second decoder coupled between the second memory array and the second sense amplifier, and configured to selectively provide a signal of the second data to the second sense amplifier according to the first address signal.

5. The memory as claimed in claim 1 , further comprising:

a writing circuit configured to store first programming data to the first memory array according to a second address signal and to store second programming data to the second memory array according to the second address signal,

wherein binary representation of the first programming data is complementary to that of the second programming data.

6. The memory as claimed in claim 1 , wherein the read circuit further comprises:

an exchange unit configured to selectively provide one of the first sensing signal and the second sensing signal as a first signal and selectively provide the other as a second signal according to the control signal,

wherein the output buffer is coupled to the exchange unit and configured to selectively provide the first signal or the second signal as the output according to the control signal.

7. The memory as claimed in claim 1 , wherein when the first memory array is a main array and the second memory array is an auxiliary array, the control signal controls the output buffer to provide the first data as the output, and when the first memory array is an auxiliary array and the second memory array is a main array, the control signal controls the output buffer to provide the second data as the output.

8. A memory, comprising:

a first memory array configured to store main data;

a second memory array configured to store complement data that is complementary to the main data; and

a read circuit, comprising:

a sensing circuit configured to provide a first sensing signal according to a reference signal and a first signal, and a second sensing signal according to the reference signal and a second signal;

a twist circuit configured to selectively provide one of first data of the main data corresponding to a first address signal and second data of the complement data corresponding to the first address signal as the first signal and selectively provide the other as the second signal according to a first control signal;

a random number generator configured to generate the first control signal and a second control signal; and

an output buffer configured to selectively provide the first sensing signal or the second sensing signal as an output according to the second control signal.

9. The memory as claimed in claim 8 , wherein the read circuit further comprises:

a first decoder coupled between the first memory array and the twist circuit configured to provide the first data from the first memory array according the first address signal; and

a second decoder coupled between the second memory array and the twist circuit configured to provide the second data from the second memory array according the first address signal.

10. The memory as claimed in claim 9 , wherein the first decoder comprises:

a first selector coupled between the first memory array and the twist circuit, and configured to selectively provide a signal of the first data stored in the first memory array to the twist circuit according to the first address signal,

wherein the second decoder comprises:

a second selector coupled between the second memory array and the twist circuit, and configured to selectively provide a signal of the second data stored in the second memory array to the twist circuit according to the first address signal,

wherein the signal of the first data stored in the first memory array is complementary to the signal of the second data stored in the second memory array.

11. The memory as claimed in claim 8 , wherein the twist circuit comprises:

a third selector configured to selectively provide one of the first data and the second data as the first signal according to the first control signal; and

a fourth selector configured to selectively provide the other data of the first data and the second data as the second signal according to the first control signal.

12. The memory as claimed in claim 8 , further comprising:

a writing circuit configured to store first programming data to the first memory array according to a second address signal and to store second programming data to the second memory array according to the second address signal,

wherein binary representation of the first programming data is complementary to that of the second programming data.

13. The memory as claimed in claim 8 , wherein the number of memory cells in the first memory array is identical to the number of memory cells in the second memory array.

14. The memory as claimed in claim 8 , wherein the first control signal controls the twist circuit to provide the first data as the second signal and provide the second data as the first signal, wherein when the first memory array is a main array and the second memory array is an auxiliary array, the second control signal controls the output buffer to provide the second sensing signal as the output, and when the first memory array is an auxiliary array and the second memory array is a main array, the second control signal controls the output buffer to provide the first sensing signal as the output.

15. A read method for a memory, comprising:

storing main data into a first memory array and complement data into a second memory array of the memory, wherein the complement data is complementary to the main data;

obtaining first data from the first memory array and second data from the second memory array according an address signal;

exchanging the first data and the second data in response to a random signal; and

selectively providing the exchanged first data or the exchanged second data as an output according to a control signal.

16. The method as claimed in claim 15 , further comprising:

selectively providing one of a first sensing signal corresponding to the exchanged first data and a second sensing signal corresponding to the exchanged second data as a first signal and selectively provide the other as a second signal according to the control signal,

wherein the first signal or the second signal is provided as the output according to the control signal.

17. The method as claimed in claim 15 , wherein the number of memory cells in the first memory array is identical to the number of memory cells in the second memory array.

18. The method as claimed in claim 15 , wherein a read circuit of the memory comprises:

a first decoder coupled to the first memory array and configured to obtain the first data from the first memory array according the address signal;

a second decoder coupled to the second memory array and configured to obtain the second data from the second memory array according the address signal; and

an output buffer configured to selectively provide the exchanged first data or the exchanged second data as the output according to the control signal.

19. The method as claimed in claim 18 , wherein the read circuit of the memory further comprising:

a first sense amplifier coupled between the first decoder and the output buffer, and configured to provide a first sensing signal according to a reference signal and the exchanged first data; and

a second sense amplifier coupled between the second decoder and the output buffer, and configured to provide a second sensing signal according to the reference signal and the exchanged second data.

20. The method as claimed in claim 19 , wherein the output buffer comprises:

a selector coupled to the first sense amplifier and the second sense amplifier, and configured to selectively provide the first sensing signal or the second sensing signal as the output according to the control signal.