Memory structures having improved write endurance
A memory structure can include a memory cell and a first barrier layer having a maximum hydrogen diffusion coefficient of 1×10 −17 cm 2 /s, said first barrier layer adjacent to the memory cell to minimize contaminant movement to or from the memory cell.
1. A memory structure, comprising:
a memory cell;
a conductive channel coupled with the memory cell;
a first passivation layer over the conductive channel;
a second passivation layer between the conductive channel and the first passivation layer;
a tetraethyl orthosilicate (TEOS) layer between the conductive channel and the second passivation layer; and
a first barrier layer between the first passivation layer and the second passivation layer, the first barrier layer comprising one or more of: silicon nitride, a metal nitride, a metal oxide, and a metal carbide.
2. The memory structure of claim 1 , wherein:
the conductive channel comprises a wordline or a bitline.
3. The memory structure of claim 1 , further comprising:
an electrode between a memory element of the memory cell and the conductive channel.
4. The memory structure of claim 1 , wherein:
the memory cell includes a memory element including a phase change material and/or chalcogenide material.
5. The memory structure of claim 4 , wherein:
the chalcogenide material includes one or more of: germanium, antimony, tellurium, silicon, nickel, gallium, arsenic, silver, tin, gold, lead, bismuth, indium, selenium, oxygen, sulfur, nitrogen, and carbon.
6. The memory structure of claim 1 , wherein:
the first barrier layer includes a dopant including one or more: silicon, zirconium, hafnium, niobium, titanium, and carbon.
7. The memory structure of claim 1 , further comprising:
a second barrier layer between the conductive channel and the second passivation layer.
8. The memory structure of claim 7 , further comprising:
a tetraethyl orthosilicate (TEOS) layer between the conductive channel and the second barrier layer.
9. The memory structure of claim 8 , further comprising:
a third barrier layer between the TEOS layer and the conductive channel.
10. The memory structure of claim 7 , further comprising:
a tetraethyl orthosilicate (TEOS) layer between the second barrier layer and the second passivation layer.
11. The memory structure of claim 1 , further comprising:
a second conductive channel coupled with the memory cell; and
a second barrier layer between the second conductive channel and a second tetraethyl orthosilicate (TEOS) layer.
12. The memory structure of claim 1 , wherein:
the first barrier layer has a thickness of from about 10 nanometer (nm) to about 300 nm.
13. The memory structure of claim 1 , wherein:
the first barrier layer includes a maximum hydrogen diffusion coefficient of 1×10 −17 cm 2 /s.
14. A memory structure, comprising:
a memory cell;
a conductive channel coupled with the memory cell;
a first passivation layer over the conductive channel;
a tetraethyl orthosilicate (TEOS) layer between the conductive channel and the first passivation layer; and
a first barrier layer between the first passivation layer and the TEOS layer, the first barrier layer comprising one or more of: silicon nitride, a metal nitride, a metal oxide, and a metal carbide.
15. The memory structure of claim 14 , wherein:
the conductive channel comprises a wordline or a bitline.
16. The memory structure of claim 14 , wherein:
the memory cell includes a memory element including a phase change material and/or chalcogenide material.
17. A memory structure, comprising:
a memory cell including a non-volatile memory element, the non-volatile memory element including a chalcogenide material and/or a phase change material;
a conductive channel coupled with the memory cell;
a first passivation layer adjacent to the conductive channel;
a first barrier layer between the first passivation layer and the conductive channel, the first barrier layer including one or more of: silicon nitride, a metal nitride, a metal oxide, and a metal carbide; and
a tetraethyl orthosilicate (TEOS) layer between the conductive channel and the first barrier layer.
18. The memory structure of claim 17 , wherein:
the conductive channel comprises a wordline or a bitline.