IP Library › Granted Patent US 11,322,477
Granted Patent B2
US 11,322,477 · App. 16/896,219 · Granted May 3, 2022

Package structure and method of fabricating the same

Inventors: Ming-Fa Chen (Taichung, TW); Nien-Fang Wu (Chiayi, TW); Sung-Feng Yeh (Taipei, TW); Tzuan-Horng Liu (Taoyuan, TW); Chao-Wen Shih (Hsinchu County, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L25/0652H01L21/561H01L21/6835H01L23/3128H01L23/5385H01L23/5386H01L23/544H01L24/32H01L24/83H01L25/50H01L2223/54426H01L2224/32225H01L2224/83005H01L2224/83896H01L2225/06541H01L2225/06586
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Quick Facts
Patent No.
US 11,322,477
App. No.
16/896,219
Granted
May 3, 2022
Kind
B2
Abstract

A structure including stacked substrates, a first semiconductor die, a second semiconductor die, and an insulating encapsulation is provided. The first semiconductor die is disposed over the stacked substrates. The second semiconductor die is stacked over the first semiconductor die. The insulating encapsulation includes a first encapsulation portion encapsulating the first semiconductor die and a second encapsulation portion encapsulating the second semiconductor die.

Claims (42)

1. A structure, comprising:

stacked substrates;

a first semiconductor die disposed over the stacked substrates;

a second semiconductor die stacked over the first semiconductor die;

an insulating encapsulation comprising a first encapsulation portion encapsulating the first semiconductor die and a second encapsulation portion encapsulating the second semiconductor die; and

a bonding layer between the first semiconductor die and the second semiconductor die, wherein the first encapsulation portion is spaced apart from the second encapsulation portion by the bonding layer.

2. The structure as claimed in claim 1 , wherein an overall thickness of the stacked substrates ranges from about 1500 micrometers to about 1600 micrometers.

3. The structure as claimed in claim 1 , wherein the first encapsulation portion is disposed over the stacked substrates, and the second encapsulation portion is disposed over the first encapsulation portion and the first semiconductor die.

4. The structure as claimed in claim 1 , wherein the bonding layer comprises a dielectric layer and conductors embedded in the dielectric layer.

5. The structure as claimed in claim 1 , further comprising a backside metal layer disposed over the stacked substrates, wherein the stacked substrates are between the backside metal layer and the first semiconductor die.

6. The structure as claimed in claim 5 , wherein a thickness of the backside metal layer ranges from about 10 micrometers to about 1000 micrometers.

7. A structure, comprising:

a support substrate;

a first semiconductor die disposed over a first surface of the support substrate;

a second semiconductor die disposed over the first semiconductor die;

a first insulating encapsulation comprising a first encapsulation portion encapsulating the first semiconductor die and a second encapsulation portion encapsulating the second semiconductor die; and

a second insulating encapsulation laterally encapsulating the support substrate, the first semiconductor die, the second semiconductor die and the first insulating encapsulation.

8. The structure as claimed in claim 7 , wherein a thickness of the support substrate ranges from about 1500 micrometers to about 1600 micrometers.

9. The structure as claimed in claim 7 , wherein the first encapsulation portion is disposed over the first surface of the support substrate, and the second encapsulation portion is disposed over the first encapsulation portion and the first semiconductor die to laterally encapsulate the second semiconductor die.

10. The structure as claimed in claim 7 , wherein the first encapsulation portion is spaced apart from the second encapsulation portion by a bonding layer between the first semiconductor die and the second semiconductor die.

11. The structure as claimed in claim 7 , wherein a thickness of the metal layer ranges from about 10 micrometers to about 1000 micrometers.

12. The structure as claimed in claim 7 further comprising:

a metal layer disposed over a second surface of the support substrate, wherein the first surface is opposite to the second surface, and the metal layer is laterally encapsulated by the second insulating encapsulation.

13. A method, comprising:

bonding first semiconductor dies to a carrier, the first semiconductor dies being spaced apart from each other, and front surfaces of the first semiconductor dies facing the carrier;

forming a first encapsulation portion over the carrier to laterally encapsulating the first semiconductor dies;

removing the carrier from the front surfaces of the first semiconductor dies and the first encapsulation portion;

forming a bonding layer on the front surfaces of the first semiconductor dies and the first encapsulation portion;

bonding second semiconductor dies to the bonding layer, front surfaces of the second semiconductor dies facing the bonding layer;

forming a second encapsulation portion over the bonding layer to laterally encapsulate the second semiconductor dies; and

after forming the first encapsulation portion over the carrier to laterally encapsulating the first semiconductor dies, bonding a support substrate comprising stacked substrates to back surfaces of the first semiconductor dies and the first encapsulation portion.

14. The method as claimed in claim 13 , wherein the support substrate comprises stacked substrates fusion bonded through at least one bonding layer.

15. The method as claimed in claim 14 , wherein the support substrate is bonded to the back surfaces of the first semiconductor dies and the first encapsulation portion before removing the carrier from the front surfaces of the first semiconductor dies and the first encapsulation portion.

16. The method as claimed in claim 13 , further comprising:

forming a redistribution circuit layer on back surfaces of the second semiconductor dies and the second encapsulation portion; and

forming conductive terminals on the redistribution circuit layer.

17. The method as claimed in claim 16 , wherein the support substrate comprises a first support substrate and a second support substrate bonded to the first support substrate.

18. The method as claimed in claim 17 , wherein the first support substrate is bonded to the back surfaces of the first semiconductor dies and the first encapsulation portion before removing the carrier from the front surfaces of the first semiconductor dies and the first encapsulation portion.

19. The method as claimed in claim 18 , wherein

the second support substrate is bonded to the first support substrate after forming the redistribution circuit layer on the second semiconductor dies and the second encapsulation portion, and

the second support substrate is bonded to the back surfaces of the first semiconductor dies and the first encapsulation portion before forming the conductive terminals on the redistribution circuit layer.

20. The method as claimed in claim 18 , wherein the second support substrate is bonded to the first support substrate after forming the conductive terminals on the redistribution circuit layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 11, 2020
From: CHEN, MING-FA; WU, NIEN-FANG; YEH, SUNG-FENG; LIU, TZUAN-HORNG; SHIH, CHAO-WEN
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 052902/0210 →
Continuity (2)
Provisional Application 62906730 · Sep 27, 2019
Related Publication 20210098420A1 · Apr 1, 2021