IP Library Granted Patent US 11,416,387
Granted Patent B2
US 11,416,387 · App. 16/899,805 · Granted Aug 16, 2022

Memory system and method for controlling nonvolatile memory

Inventors: Hideki Yoshida (Yokohama Kanagawa, JP); Shinichi Kanno (Tokyo, JP)
Assignee: Kioxia Corporation
G06F12/0246G06F3/06G06F3/064G06F12/0253G06F12/06G06F12/10G06F2212/1016G06F2212/152G06F2212/2022G06F2212/7201G06F2212/7202G06F2212/7205G06F2212/7208
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Quick Facts
Patent No.
US 11,416,387
App. No.
16/899,805
Granted
Aug 16, 2022
Kind
B2
Abstract

According to one embodiment, a memory system includes a nonvolatile memory including plural blocks each including plural pages, and a controller. When receiving a write request designating a first logical address and a first block number from the host, the controller determines a first location in a first block having the first block number to which data from the host should be written, and writes the data from the host to the first location in the first block. The controller notifies the host of either an in-block physical address indicative of the first location, or a group of the first logical address, the first block number and the first in-block physical address.

Claims (82)

1. A memory system connectable to a host, comprising:

a nonvolatile memory including a plurality of blocks, each of the plurality of blocks being a unit for data erase operation, each of the plurality of blocks including a plurality of pages, each of the plurality of pages being a unit for data write operation; and

a controller electrically connected to the nonvolatile memory and configured to:

in response to receiving, from the host, a copy command that includes a first identifier and a second identifier:

determine first data in a first block among the plurality of blocks, the first data corresponding to the first identifier included in the copy command;

determine second data in a second block among the plurality of blocks, the second data corresponding to the second identifier included in the copy command;

determine a third block among the plurality of blocks;

determine a first page among the plurality of pages of the third block;

determine a second page among the plurality of pages of the third block;

copy (A) the first data from the first block to the first page of the third block and (B) the second data from the second block to the second page of the third block; and

notify the host of:

a third identifier corresponding to the third block;

a fourth identifier corresponding to the first page of the third block; and

a fifth identifier corresponding to the second page of the third block.

2. The memory system according to claim 1 , wherein

the copy command further includes a third identifier, and

the controller is configured to determine the third block on the basis of the third identifier included in the copy command.

3. The memory system according to claim 1 , wherein

the fourth identifier and the fifth identifier are not included in the copy command.

4. The memory system according to claim 1 , wherein

the controller is further configured to:

write, into the third block, a first logical address associated with the first data; and

write, into the third block, a second logical address associated with the second data.

5. The memory system according to claim 4 , wherein

the controller is further configured to notify the host of:

the first logical address associated with the first data; and

the second logical address associated with the second data.

6. The memory system according to claim 1 , wherein

the controller is further configured to transmit, to the host, a completion response for the copy command, and

in response to the completion response, the host updates a mapping table to map (A) a first logical address to the third identifier and (B) a second logical address to the third identifier, the first logical address being associated with the first data, and the second logical address being associated with the second data.

7. The memory system according to claim 1 , wherein

the copy command is issued for garbage collection operation.

8. A memory system connectable to a host, comprising:

a nonvolatile memory including a plurality of blocks, each of the plurality of blocks being a unit for data erase operation; and

a controller electrically connected to the nonvolatile memory and configured to:

in response to receiving, from the host, a copy command that includes a first identifier and a second identifier:

determine first data in a first block among the plurality of blocks, the first data corresponding to the first identifier included in the copy command;

determine second data in a second block among the plurality of blocks, the second data corresponding to the second identifier included in the copy command;

determine a third block among the plurality of blocks;

copy (A) the first data from the first block to the third block and (B) the second data from the second block to the third block;

write, into the third block, a first logical address associated with the first data; and

write, into the third block, a second logical address associated with the second data.

9. The memory system according to claim 8 , wherein

the copy command further includes a third identifier, and

the controller is configured to determine the third block on the basis of the third identifier included in the copy command.

10. The memory system according to claim 8 , wherein

each of the plurality of blocks includes a plurality of pages, each of the plurality of pages being a unit for data write operation, and

the controller is further configured to:

determine a first page among the plurality of pages of the third block;

determine a second page among the plurality of pages of the third block; and

copy (A) the first data from the first block to the first page of the third block and (B) the second data from the second block to the second page of the third block.

11. The memory system according to claim 8 , wherein

the controller is further configured to notify the host of:

a third identifier corresponding to the third block;

the first logical address associated with the first data; and

the second logical address associated with the second data.

12. The memory system according to claim 8 , wherein

the controller is further configured to transmit, to the host, a completion response for the copy command, and

in response to the completion response, the host updates a mapping table to map (A) the first logical address to a third identifier and (B) the second logical address to the third identifier, the third identifier corresponding to the third block.

13. The memory system according to claim 8 , wherein

the copy command is issued for garbage collection operation.

14. A memory system connectable to a host, comprising:

a nonvolatile memory including a plurality of blocks, each of the plurality of blocks being a unit for data erase operation; and

a controller electrically connected to the nonvolatile memory and configured to:

in response to receiving, from the host, a copy command that includes a first identifier and a second identifier:

determine first data in a first block among the plurality of blocks, the first data corresponding to the first identifier included in the copy command;

determine second data in a second block among the plurality of blocks, the second data corresponding to the second identifier included in the copy command;

determine a third block among the plurality of blocks;

copy (A) the first data from the first block to the third block and (B) the second data from the second block to the third block; and

transmit, to the host, a completion response for the copy command, wherein

in response to the completion response, the host updates a mapping table to map (A) a first logical address to a third identifier and (B) a second logical address to the third identifier, the first logical address being associated with the first data, the second logical address being associated with the second data, and the third identifier corresponding to the third block.

15. The memory system according to claim 14 , wherein

the copy command further includes the third identifier, and

the controller is configured to determine the third block on the basis of the third identifier included in the copy command.

16. The memory system according to claim 14 , wherein

each of the plurality of blocks includes a plurality of pages, each of the plurality of pages being a unit for data write operation, and

the controller is further configured to:

determine a first page among the plurality of pages of the third block;

determine a second page among the plurality of pages of the third block; and

copy (A) the first data from the first block to the first page of the third block and (B) the second data from the second block to the second page of the third block.

17. The memory system according to claim 14 , wherein

the copy command is issued for garbage collection operation.

Assignments (3)
MERGER AND CHANGE OF NAME Recorded Feb 17, 2022
From: TOSHIBA MEMORY CORPORATION; K.K. PANGEA
To: K.K. PANGEA
Reel/Frame 059039/0780 →
CHANGE OF NAME Recorded Feb 17, 2022
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 059175/0001 →
CHANGE OF NAME Recorded Feb 17, 2022
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 059180/0266 →
Priority Claims (1)
JP JP2017-208105 · Oct 27, 2017 · national
Continuity (2)
Continuation 15984944 · May 21, 2018
Related Publication 20200310961A1 · Oct 1, 2020