Neighbor aware multi-bias programming in scaled BICS
View Patent ↗A storage device may be configured to determine data states for a first set of memory cells, of an array of memory cells, that are part of a logical N−1 neighboring word line that is adjacent to a selected word line. The storage device may be further configured to determine a program voltage configuration based on the data states. The storage device may be further configured to determine, using the program voltage configuration, a program operation on the selected word line to iteratively program respective memory cells, of a second set of memory cells that are part of the selected word line. Determining the data states, determining the program voltage configuration, and performing the program operation may be repeated until a program stop condition is satisfied.
1. A method of programming an array of memory cells formed using a set of word lines and a set of bit lines, the method comprising:
determining data states for a first set of memory cells, of the array of memory cells, that are part of a logical N−1 neighboring word line that is adjacent to a selected word line;
determining bit line voltage biases based on the data states; and
performing, using the bit line voltage biases, a program operation on the selected word line to iteratively program respective memory cells, of a second set of memory cells that are part of the selected word line, wherein performing the program operation comprises:
causing a first bit line voltage bias to be applied to a first subset of the first set of memory cells based on the first subset having neighboring memory cells in an erased data state, and
causing a second bit line voltage bias, that is higher than the first bit line voltage bias, to be applied to a second subset of the first set of memory cells based on the second subset having neighboring memory cells in a programmed data state, the first bit line voltage bias and the second bit line voltage bias to eliminate or reduce a natural threshold voltage distribution (NVD) split of the selected word line,
wherein determining the data states, determining the program voltage configuration, and performing the program operation are to be repeated until a program stop condition is satisfied.
2. The method as set forth in claim 1 , wherein performing the program operation comprises:
causing a modified program voltage to be applied to the selected word line during a first iteration of the program operation, the modified program voltage having a value based on a natural threshold voltage distribution (NVD) split associated with the selected word line.
3. The method as set forth in claim 1 , further comprising:
performing a verify operation that includes verifying data states of the respective memory cells, of the second set of memory cells, during select iterations of the verify operation, wherein a frequency at which to verify the data states is based on a natural threshold voltage distribution (NVD) for the selected word line.
4. The method as set forth in claim 1 , wherein the first set of memory cells are programmed using a normal order programming (NOP) scheme and the logical N−1 neighboring word line is a physical N−1 neighboring word line.
5. The method as set forth in claim 1 , wherein the first set of memory cells are programmed using a reverse order programming (ROP) scheme and the logical N−1 neighboring word line is a physical N+1 neighboring word line.
6. The method as set forth in claim 1 , wherein the array of memory cells are part of a group of at least 20 NAND memory strings included in bit cost scalable (BiCS) architecture.