IP Library › Granted Patent US 11,552,074
Granted Patent B2
US 11,552,074 · App. 16/900,996 · Granted Jan 10, 2023

Package structures and methods of fabricating the same

Inventors: Ming-Fa Chen (Taichung, TW); Sung-Feng Yeh (Taipei, TW); Tzuan-Horng Liu (Taoyuan, TW); Chao-Wen Shih (Hsinchu County, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L27/0688H01L21/76877H01L21/78H01L23/5384
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Quick Facts
Patent No.
US 11,552,074
App. No.
16/900,996
Granted
Jan 10, 2023
Kind
B2
Abstract

A package structure and a method of fabricating the same are provided. The method includes bonding a first die and a second die to a wafer in a first die region of the wafer hybrid bonding; bonding a first dummy structure to the wafer in the first die region and a first scribe line of the wafer; and singulating the wafer and the first dummy structure along the first scribe line to form a stacked integrated circuit (IC) structure.

Claims (36)

1. A method comprising:

bonding a first die and a second die to a wafer in a first die region of the wafer through hybrid bonding;

bonding a first dummy structure to the wafer in the first die region; and

singulating the wafer and the first dummy structure along a first scribe line to form a stacked integrated circuit (IC) structure,

wherein the first dummy structure has a continuous ring shape surrounding the first die region.

2. The method of claim 1 , wherein the first dummy structure is bonded in an area surrounded by the first die, the second die, the first scribe line and a second scribe line of the wafer, and extends to a second die region.

3. The method of claim 1 , wherein the first dummy structure extends from the first die region to a second die region of the wafer.

4. The method of claim 1 , wherein the first dummy structure overlaps the first scribe line and a second scribe line of the wafer, and the first scribe line and the second scribe are along different directions.

5. The method of claim 4 , further comprising:

bonding a second dummy structure to the wafer in a second die region and the first scribe line of the wafer; and

bonding a third dummy structure to the wafer in a third region and the second scribe line of the wafer.

6. The method of claim 1 , wherein the first dummy completely surrounds each of the first die and the second die.

7. The method of claim 6 , wherein the wafer comprises a third die having a second insulating layer, and the first dummy structure is boned to the third die through fusion bonding the first insulating layer and the second insulating layer, and the hybrid bonding comprises metal-to-metal direct bonding and dielectric-to-dielectric bonding.

8. The method of claim 1 , wherein the first dummy structure is a dummy die, and the dummy die includes a silicon substrate and a first insulating layer on the silicon substrate.

9. A method comprising:

bonding a first die and a second die to a wafer in a die region of the wafer;

bonding a first dummy structure to the wafer in the die region to overlay a plurality of corners of the die region; and

singulating the wafer to form a stacked integrated circuit (IC) structure,

wherein the first dummy structure comprises a first portion and a second portion connected each other and extended along different directions, and

wherein the first dummy structure is a dummy die, and the dummy die includes a silicon substrate and a first insulating layer on the silicon substrate.

10. The method of claim 9 , wherein the wafer comprises:

a third die having a second insulating layer, and the first dummy structure is boned to the third die through fusion bonding a first insulating layer and the second insulating layer, and the first die and the second die are bonded to the third die through hybrid bonding, and the hybrid bonding comprises metal-to-metal direct bonding and dielectric-to-dielectric bonding.

11. The method of claim 9 , wherein the first dummy structure has a rectangular shape or a ring shape in a top view.

12. The method of claim 9 , further comprising:

bonding a second dummy structure to the wafer in the die region, wherein the first dummy structure is adjacent to a first scribe line of the wafer and the second dummy structure is adjacent to a second scribe line of the wafer, and the first scribe line and the second scribe line are along different directions.

13. A method comprising:

bonding first dies and second dies to a wafer in a first die region and a second die region of the wafer, wherein the first die region comprises a first one of the first dies and a first one of the second dies, and the second die region comprises a second one of the first dies and a second one of the second dies;

bonding a first dummy structure to the wafer, wherein the first dummy structure spans from the first die region to the second die region of the wafer, the first dummy structure is located between the first one and the second one of the second dies, and the first dies are arranged side by side without a dummy structure in between; and

singulating the wafer and the first dummy structure along a first scribe line to form a stacked integrated circuit (IC) structure.

14. The method of claim 13 , further comprising an encapsulate surrounding the first dies, the second dies and the first dummy structure.

15. The method of claim 13 , wherein the first dummy structure has a rectangular shape in a top view.

16. The method of claim 13 , wherein a sidewall of the first dummy structure is flushed with sidewalls of the first one and the second one of the second dies.

17. The method of claim 13 , further comprising bonding a second dummy structure to the wafer, wherein the first dummy structure and the second dummy structure are located at opposite sides of the first one of the second dies.

18. The method of claim 13 , wherein bonding the first dummy structure to the wafer comprises a fusion bonding.

19. The method of claim 13 , wherein bonding the first dies and the second dies to the wafer comprises a hybrid bonding.

20. The method of claim 19 , wherein the hybrid bonding comprises metal-to-metal direct bonding and dielectric-to-dielectric bonding.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 18, 2020
From: CHEN, MING-FA; YEH, SUNG-FENG; LIU, TZUAN-HORNG; SHIH, CHAO-WEN
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 052970/0297 →
Continuity (1)
Related Publication 20210391322A1 · Dec 16, 2021
Cited By (1)
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