Epitaxial source/drain feature with enlarged lower section interfacing with backside via

1. A method comprising:

providing a structure having a substrate, an isolation structure over the substrate, a fin extending from the substrate and adjacent to the isolation structure, a sacrificial gate structure disposed over a channel region of the fin, and gate spacers on opposing sidewalls of the sacrificial gate structure;

first etching the fin adjacent the gate spacers to form a first source/drain (S/D) trench on one side of the sacrificial gate structure and a second S/D trench on another side of the sacrificial gate structure;

forming an etch mask that exposes the first S/D trench and covers the second S/D trench;

second etching the fin through the etch mask to deepen the first S/D trench; and

after the second etching, laterally etching a portion of the isolation structure that is exposed at a lower section of the first S/D trench, resulting in an expanded lower section of the first S/D trench, wherein the laterally etching is tuned selective to a material of the isolation structure and not to a material of the fin.

2. The method of claim 1 , further comprising:

after the laterally etching, epitaxially growing a first semiconductor layer in at least the expanded lower section of the first S/D trench.

3. The method of claim 2 , further comprising:

epitaxially growing a first semiconductor S/D feature over the first semiconductor layer.

4. The method of claim 3 , wherein the isolation structure is disposed over a frontside of the substrate, further comprising:

thinning down the substrate from a backside of the substrate opposite to the frontside, thereby exposing the first semiconductor layer and the fin from the backside.

5. The method of claim 4 , further comprising:

etching the first semiconductor layer from the backside to expose the first semiconductor S/D feature, resulting in a via hole; and

forming a metal plug in the via hole.

6. The method of claim 5 , further comprising:

forming a metal track on the backside, the metal track electrically connecting to the metal plug.

7. The method of claim 1 , wherein the expanded lower section of the first S/D trench is narrower at an upper portion than at a lower portion.

8. The method of claim 1 , wherein the fin includes a stack of second and third semiconductor layers, further comprising:

before the forming of the etch mask, recessing the second semiconductor layers within at least the first S/D trench to form gaps, and forming an inner dielectric spacer in the gaps.

9. A method comprising:

providing a structure having a substrate, an isolation structure over the substrate, a fin extending from the substrate and adjacent to the isolation structure, a sacrificial gate structure disposed over a channel region of the fin, and gate spacers on opposing sidewalls of the sacrificial gate structure, wherein the fin includes a stack of second and third semiconductor layers;

first etching the fin adjacent the gate spacers to form a first source/drain (S/D) trench on one side of the sacrificial gate structure and a second S/D trench on another side of the sacrificial gate structure;

recessing the second semiconductor layers within at least the first S/D trench to form gaps;

forming an inner dielectric spacer in the gaps;

after the forming of the inner dielectric spacer, forming an etch mask that exposes the first S/D trench and covers the second S/D trench;

second etching the fin through the etch mask to deepen the first S/D trench;

after the second etching, laterally etching a portion of the isolation structure that is exposed at a lower section of the first S/D trench, resulting in an expanded lower section of the first S/D trench;

growing a first semiconductor layer in at least the expanded lower section of the first S/D trench, wherein the first semiconductor layer includes a different material than the fin; and

epitaxially growing a first semiconductor S/D feature over the first semiconductor layer.

10. The method of claim 9 , further comprising:

replacing the sacrificial gate structure with a high-k metal gate.

11. The method of claim 10 , further comprising:

forming a S/D contact over the first semiconductor S/D feature.

12. The method of claim 11 , wherein the isolation structure is disposed over a frontside of the substrate, further comprising:

thinning down the substrate from a backside of the substrate opposite to the frontside, thereby exposing the first semiconductor layer and the fin from the backside;

removing the fin to form second trenches;

depositing one or more dielectric materials in the second trenches;

etching the first semiconductor layer to form a via hole; and

forming a metal plug in the via hole.

13. The method of claim 12 , wherein the metal plug has a profile that widens and then narrows along a vertical direction.

14. A method comprising:

providing a structure having a substrate, an isolation structure over the substrate, a fin extending from the substrate and adjacent to the isolation structure, a sacrificial gate structure disposed over a channel region of the fin, and gate spacers on opposing sidewalls of the sacrificial gate structure, wherein the fin includes a stack of first and second semiconductor layers;

first etching the fin adjacent the gate spacers to form a first source/drain (S/D) trench on one side of the sacrificial gate structure and a second S/D trench on another side of the sacrificial gate structure;

recessing the first semiconductor layers within at least the first S/D trench to form gaps;

forming an inner dielectric spacer in the gaps;

forming an etch mask that exposes the first S/D trench and covers the second S/D trench;

second etching the fin through the etch mask to deepen the first S/D trench;

after the second etching, laterally etching a portion of the isolation structure that is exposed at a lower section of the first S/D trench, resulting in an expanded lower section of the first S/D trench; and

growing a third semiconductor layer in at least the expanded lower section of the first S/D trench.

15. The method of claim 14 , further comprising:

epitaxially growing a semiconductor S/D feature over the third semiconductor layer.

16. The method of claim 15 , further comprising:

replacing the sacrificial gate structure with a functional gate.

17. The method of claim 15 , further comprising:

thinning down the substrate from a backside of the substrate opposite to a side where the sacrificial gate structure is disposed, thereby exposing the third semiconductor layer and the fin from the backside;

selectively etching the fin to form second trenches; and

depositing one or more dielectric materials in the second trenches that partly surround the third semiconductor layer.

18. The method of claim 17 , further comprising:

selectively etching the third semiconductor layer to form a via hole that is partly surrounded by the one or more dielectric materials, thereby exposing the semiconductor S/D feature.

19. The method of claim 18 , further comprising:

forming a silicide layer over the semiconductor S/D feature and in the via hole.

20. The method of claim 18 , further comprising:

forming a metal plug in the via hole; and

forming a power rail on the metal plug and electrically connected to the metal plug.