Field effect transistor with source/drain via and method
A device includes a substrate, a vertical stack of nanostructure channels over the substrate, a gate structure wrapping around the nanostructure channels, and a source/drain region on the substrate. The device further includes a source/drain contact in contact with the source/drain region. The source/drain contact includes a core layer of a first material. A source/drain via is over and in contact with the source/drain contact. The source/drain via is the first material. A gate via is over and in electrical connection with the gate structure. The gate via is the first material.
1 . A method comprising:
forming a stack of nanostructure channels over a substrate;
forming a gate structure wrapping around the stack;
forming a source/drain region on the substrate;
forming an opening exposing the source/drain region;
forming a silicide region in the source/drain region by a first annealing operation;
forming a core layer in the opening on the silicide region by depositing a metal in the opening, and annealing the metal by a second annealing operation; and
forming a source/drain via over and contacting the core layer, a material of the source/drain via being the same as that of the core layer.
2 . The method of claim 1 , wherein the forming a silicide region includes:
forming a first metal layer in the opening and contacting the source/drain region; and
annealing the first metal layer by the first annealing operation.
3 . The method of claim 2 , further comprising:
forming a first liner layer in the opening;
exposing the source/drain region by removing material of the first liner layer at a bottom of the opening;
wherein the first metal layer is formed on sidewalls of the first liner layer.
4 . The method of claim 3 , wherein:
the first liner layer is formed on sidewalls of a second interlayer dielectric overlying the gate structure and the source/drain region; and
the first metal layer is formed on the first liner layer and on the sidewalls and a top of the second interlayer dielectric.
5 . The method of claim 4 , further comprising:
planarizing an upper surface of the core layer; and
forming a second etch stop layer on the core layer, the second interlayer dielectric, and a portion of the first metal layer on the sidewall of the second interlayer dielectric.
6 . The method of claim 1 , further comprising:
forming a conductive layer on the gate structure;
forming a gate capping structure on the conductive layer; and
forming a gate via that extends through the gate capping structure and is in contact with the conductive layer, the gate via and the source/drain via being formed by a same deposition operation.
7 . A method comprising:
forming, over a substrate, a vertical stack of nanostructure channels, a gate structure wrapping around the stack, and a conductive layer on an upper surface of the gate structure;
forming a source/drain region laterally adjacent the gate structure;
etching a contact opening that exposes the source/drain region;
conformally depositing a first liner on sidewalls of the contact opening;
depositing a second liner of a metal precursor on the first liner and on the exposed source/drain region;
annealing to convert the second liner to a silicide region;
continuing deposition of the same metal until the contact opening is filled with a core layer of the metal;
planarizing the core layer;
depositing a second etch-stop layer;
depositing a second ILD over the second etch-stop layer;
etching a source/drain-via opening terminating on the core layer and a gate-via opening terminating on the conductive layer; and
filling the source/drain via opening and the gate via opening with the same metal; and
annealing so that the core layer and both vias form a continuous, seam-free metal structure.
8 . The method of claim 7 , wherein the silicide region comprises TiSi, TiNiSi, WSi, or CoSi.
9 . The method of claim 7 , wherein the first liner is SiN, SiCN, SiOCN, or SiOC.
10 . The method of claim 7 , wherein the first liner is deposited on sidewalls of dielectric layers defining the contact opening.
11 . The method of claim 7 , further comprising depositing a gate-capping dielectric over the conductive layer before depositing the second ILD.
12 . The method of claim 7 , wherein the source/drain contact has an aspect ratio between 1 and 8.
13 . The method of claim 7 , wherein the annealing is performed at 200-450° C. for one to ten minutes.
14 . A method comprising:
forming a stack of nanostructure channels over a substrate;
forming a gate structure wrapping around the stack;
forming a source/drain region on the substrate;
forming a contact opening exposing the source/drain region;
forming a silicide region in the source/drain region by a first annealing operation;
forming a core layer in the opening on the silicide region by depositing a metal in the opening, and annealing the metal by a second annealing operation;
forming a source/drain via over and contacting the core layer, a material of the source/drain via being the same as that of the core layer; and
annealing so that the core layer and the source/drain via form a continuous, seam-free metal structure.
15 . The method of claim 14 , wherein the contact opening has an aspect ratio between 1 and 8.
16 . The method of claim 14 , wherein the first annealing operation is performed at 200° C. to 450° C. for one to ten minutes.
17 . The method of claim 14 , further comprising conformally depositing a first liner on sidewalls of the contact opening before depositing the metal.
18 . The method of claim 17 , wherein the first liner comprises SiN, SiCN, SiOCN, or SiOC.
19 . The method of claim 14 , wherein the silicide region comprises TiSi, TiNiSi, WSi, or CoSi.
20 . The method of claim 14 , further comprising:
forming a conductive layer on the gate structure;
forming a gate capping structure on the conductive layer; and
forming a gate via that extends through the gate capping structure and is in contact with the conductive layer, the gate via and the source/drain via being formed by a same deposition operation.