Method and structure for reducing source/drain contact resistance at wafer backside
A method provides a structure having a fin oriented lengthwise and widthwise along first and second directions respectively, an isolation structure adjacent to sidewalls of the fin, and first and second source/drain (S/D) features over the fin. The method includes forming an etch mask exposing a first portion of the fin under the first S/D feature and covering a second portion of the fin under the second S/D feature; removing the first portion of the fin, resulting in a first trench; forming a first dielectric feature in the first trench; and removing the second portion of the fin to form a second trench. The first dielectric feature and the isolation structure form first and second sidewalls of the second trench respectively. The method includes laterally etching the second sidewalls, thereby expanding the second trench along the second direction and forming a via structure in the expanded second trench.
1. A method, comprising:
providing a structure including a fin oriented lengthwise along a first direction and widthwise along a second direction perpendicular to the first direction, an isolation structure adjacent to sidewalls of the fin, and first and second source/drain (S/D) features over the fin;
forming an etch mask exposing a first portion of the fin under the first S/D feature and covering a second portion of the fin under the second S/D feature;
removing the first portion of the fin through the etch mask, resulting in a first trench;
forming a first dielectric feature in the first trench;
removing the second portion of the fin to form a second trench, wherein the first dielectric feature forms first sidewalls of the second trench and the isolation structure forms second sidewalls of the second trench;
laterally etching the second sidewalls of the second trench, thereby expanding the second trench along the second direction; and
after the laterally etching, forming a via structure in the second trench.
2. The method of claim 1 , after the forming of the first dielectric feature, further comprising:
removing the etch mask before the removing of the second portion of the fin.
3. The method of claim 1 , wherein the laterally etching is tuned selective to a material of the isolation structure and not a material of the first dielectric feature.
4. The method of claim 1 , wherein the laterally etching widens a width of the second trench by about 10% to about 40% as measured at a top surface of the isolation structure and along the second direction.
5. The method of claim 1 , wherein the laterally etching exposes a void partially surrounded by the isolation structure, the second S/D feature, and a dielectric fin adjoining the second S/D feature.
6. The method of claim 5 , wherein the via structure fills the void.
7. The method of claim 1 , wherein the laterally etching further cleans surfaces of the second S/D feature exposed in the second trench.
8. The method of claim 1 , wherein the laterally etching includes an isotropic etching component and an anisotropic etching component.
9. The method of claim 1 , wherein the second S/D feature is a source feature of a transistor.
10. A method, comprising:
providing a structure including a substrate, a fin over the substrate, an isolation structure over the substrate and adjacent to sidewalls of the fin, and first and second source/drain (S/D) features over the fin;
thinning down the substrate until the fin is exposed;
forming an etch mask exposing a first portion of the fin under the first S/D feature and covering a second portion of the fin under the second S/D feature;
removing the first portion of the fin through the etch mask, resulting in a first trench;
forming a first dielectric feature in the first trench;
removing the second portion of the fin, resulting in a second trench, wherein the first dielectric feature forms first sidewalls of the second trench, the isolation structure forms second sidewalls of the second trench, and the first and the second sidewalls of the second trench include different materials;
laterally etching the second sidewalls of the second trench, wherein the laterally etching is tuned selective to a material of the second sidewalls of the second trench but not a material of the first sidewalls of the second trench; and
after the laterally etching, forming a silicide feature on surfaces of the second S/D feature exposed in the second trench.
11. The method of claim 10 , wherein the removing of the first portion of the fin includes applying an anisotropic etching process to the first portion of the fin, and the removing of the second portion of the fin includes applying an isotropic etching process to the second portion of the fin.
12. The method of claim 10 , wherein the laterally etching includes both an isotropic etching process and an anisotropic etching process.
13. The method of claim 10 , wherein the isolation structure includes silicon dioxide, and the laterally etching includes applying at least one of NF 3 , NH 3 , and HF.
14. The method of claim 10 , further comprising:
forming a via structure in the second trench and over the silicide feature.
15. The method of claim 10 , wherein the laterally etching widens a width of the second trench by about 10% to about 40% as measured at a top surface of the isolation structure and along a widthwise direction of the fin.
16. The method of claim 10 , wherein the laterally etching widens a width of the second trench by about 2 nm to about 10 nm per side as measured at a top surface of the isolation structure and along a widthwise direction of the fin.
17. A method, comprising:
providing a structure including an isolation structure, a semiconductor fin extending in the isolation structure and oriented lengthwise along a first direction and widthwise along a second direction perpendicular to the first direction, and one or more source/drain (S/D) features below the semiconductor fin;
forming an etch mask over the semiconductor fin, wherein the etch mask exposes a first portion of the semiconductor fin and covers a second portion of the semiconductor fin;
etching the first portion of the semiconductor fin through the etch mask, resulting in a first trench;
forming one or more first dielectric layers in the first trench;
etching the second portion of the semiconductor fin without using another etch mask, thereby forming a second trench; and
laterally etching sidewalls of the second trench, thereby expanding the second trench along the second direction.
18. The method of claim 17 , wherein the one or more first dielectric layers form first sidewalls of the second trench, the isolation structure forms second sidewalls of the second trench, and the laterally etching is tuned selective to a material of the second sidewalls of the second trench.
19. The method of claim 18 , wherein the laterally etching includes an isotropic etching component and an anisotropic etching component.
20. The method of claim 17 , wherein the etching of the second portion of the semiconductor fin includes applying an isotropic etching process to the second portion of the semiconductor fin.