Method of forming semiconductor device with silicide layer with different silicide phases or different thicknesses
A method of forming a semiconductor device includes the following steps. A substrate is patterned to form a fin structure. The fin structure is recessed to form a recess in the fin structure. An epitaxial source/drain region is grown from the recess. A first silicide layer is formed on the epitaxial source/drain region. A first portion of the first silicide layer is thinned, while leaving a second portion of the first silicide layer un-thinned. A metal contact is formed in contact with the thinned first portion of the first silicide layer.
1 . A method of forming a semiconductor device, comprising:
patterning a substrate to form a fin structure;
recessing the fin structure to form a recess in the fin structure;
growing an epitaxial source/drain region from the recess;
forming a first silicide layer on the epitaxial source/drain region;
thinning a first portion of the first silicide layer, while leaving a second portion of the first silicide layer un-thinned, wherein the first portion has a top surface lower than a top surface of the second portion; and
forming a metal contact in contact with the thinned first portion of the first silicide layer.
2 . The method of claim 1 , wherein the metal contact has a bottommost surface in contact with the first silicide layer.
3 . The method of claim 1 , further comprising:
doping the thinned first portion of the first silicide layer with a dopant; and
after doping the thinned first portion of the first silicide layer, annealing the first silicide layer.
4 . The method of claim 3 , wherein the dopant comprises B, P, As, Sb, Ga, F, C, N, Ar, He, H, Cl, Si, Ge, or a combination thereof.
5 . The method of claim 3 , wherein after annealing the first silicide layer, the thinned first portion of the first silicide layer has a Ti 5 Si 4 phase.
6 . The method of claim 5 , wherein after annealing the first silicide layer, the thinned first portion of the first silicide layer has a silicide phase different from a silicide phase of the un-thinned second portion of the first silicide layer.
7 . The method of claim 1 , wherein thinning the first portion of the first silicide layer is performed such that the epitaxial source/drain region is exposed.
8 . The method of claim 7 , further comprising:
forming a second silicide layer on the epitaxial source/drain region after thinning the first portion of the first silicide layer.
9 . The method of claim 8 , wherein the second silicide layer has a silicide phase different from a silicide phase of the first silicide layer.
10 . The method of claim 1 , wherein thinning the first portion of the first silicide layer is performed such that a portion of the epitaxial source/drain region is removed.
11 . The method of claim 1 , wherein the un-thinned second portion of the first silicide layer is a side portion of the first silicide layer.
12 . The method of claim 1 , wherein the metal contact has a bottom surface lower than a topmost position of the first silicide layer.
13 . A method of forming a semiconductor device, comprising:
forming a multi-layer stack on a substrate, wherein the multi-layer stack comprises alternately stacked first semiconductor layers and second semiconductor layers;
etching the multi-layer stack and the substrate to form fin structures each comprising alternately stacked first nanostructures and second nanostructures;
forming a dummy gate stack across the fin structures;
forming epitaxial source/drain regions on opposite sides of the dummy gate stack;
forming a first silicide layer on one of the epitaxial source/drain regions, wherein the first silicide layer has a first silicide phase;
forming an interlayer dielectric (ILD) layer on the epitaxial source/drain regions and the dummy gate stack;
replacing the first nanostructures with a metal gate stack;
etching the ILD layer to expose the first silicide layer;
thinning a first portion of the first silicide layer, while leaving a second portion of the first silicide layer un-thinned, wherein thinning the first portion of the first silicide layer is performed such that the epitaxial source/drain regions are exposed;
forming a second silicide layer on the epitaxial source/drain regions having a second silicide phase different from the first silicide phase; and
forming a metal contact on the first silicide layer.
14 . The method of claim 13 , wherein the second silicide phase has a contact resistance lower than a contact resistance of the first silicide phase.
15 . The method of claim 13 , wherein the first silicide phase is a C49-TiSi 2 phase or a C54-TiSi 2 phase.
16 . The method of claim 13 , wherein the second silicide phase is a Ti 5 Si 4 phase.
17 . The method of claim 13 , wherein during annealing the first silicide layer, the first silicide layer has a side portion having a silicide phase being substantially intact.
18 . A semiconductor device, comprising:
a fin structure protruding from a substrate;
a gate stack crossing the fin structure;
epitaxial source/drain regions on opposite sides of the gate stack;
a first silicide layer covering a top of at least one of the epitaxial source/drain regions, wherein the first silicide layer has a bottom surface lower than a top surface of the epitaxial source/drain regions;
a second silicide layer along a sidewall of the at least one of the epitaxial source/drain regions, wherein the second silicide layer and the first silicide layer are different in thickness or in silicide phase; and
a source/drain contact over the first silicide layer.
19 . The semiconductor device of claim 18 , wherein the first silicide layer and the second silicide layer have a thickness difference in a range from about 1 nm to about 5 nm.
20 . The semiconductor device of claim 18 , wherein the first silicide layer has a contact resistance lower than a contact resistance of the second silicide layer.