Vertical semiconductor device with enhanced contact structure and associated methods
A vertical semiconductor device may include a semiconductor substrate having at least one trench therein, and a superlattice liner at least partially covering sidewall portions of the at least one trench and defining a gap between opposing sidewall portions of the superlattice liner. The superlattice liner may include a plurality of stacked groups of layers, each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer, with each at least one non-semiconductor monolayer of each group being constrained within a crystal lattice of adjacent base semiconductor portions. The device may also include a semiconductor layer on the superlattice liner and including a dopant constrained therein by the superlattice liner, and a conductive body within the at least one trench defining a source contact.
1. A vertical semiconductor device comprising:
a semiconductor substrate having at least one trench therein;
a superlattice liner at least partially covering sidewall portions of the at least one trench and defining a gap between opposing sidewall portions of the superlattice liner, the superlattice liner comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer, with each at least one non-semiconductor monolayer of each group of layers being constrained within a crystal lattice of adjacent base semiconductor portions;
a semiconductor layer on the superlattice liner and comprising a dopant constrained therein by the superlattice liner; and
a conductive body within the at least one trench defining a source contact.
2. The vertical semiconductor device of claim 1 wherein the conductive body comprises a metal liner adjacent the semiconductor layer and comprising a first metal, and a metal body adjacent the metal liner, filling the at least one trench and comprising a second metal.
3. The vertical semiconductor device of claim 2 wherein the conductive body comprises silicide.
4. The vertical semiconductor device of claim 2 wherein the semiconductor layer comprises silicon; and the first metal comprises at least one of titanium, cobalt and nickel.
5. The vertical semiconductor device of claim 2 wherein the second metal comprises tungsten.
6. The vertical semiconductor device of claim 1 wherein the base semiconductor monolayers comprise silicon.
7. The vertical semiconductor device of claim 1 wherein the at least one non-semiconductor monolayer comprises oxygen.
8. The vertical semiconductor device of claim 1 wherein the superlattice liner also covers bottom portions of the at least one trench.
9. The vertical semiconductor device of claim 1 wherein the at least one trench comprises a plurality of trenches.
10. A vertical semiconductor device comprising:
a semiconductor substrate having at least one trench therein;
a superlattice liner at least partially covering sidewall portions of the at least one trench, the superlattice liner comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer, with each at least one non-semiconductor monolayer of each group of layers being constrained within a crystal lattice of adjacent base semiconductor portions;
a semiconductor layer on the superlattice liner and comprising a dopant constrained therein by the superlattice liner; and
a conductive body within the at least one trench defining a source contact and comprising
a metal liner adjacent the semiconductor layer and comprising titanium, and
a tungsten body adjacent the metal liner and filling the at least one trench.
11. The vertical semiconductor device of claim 10 wherein the conductive body comprises silicide.
12. The vertical semiconductor device of claim 10 wherein the semiconductor layer comprises silicon.
13. The vertical semiconductor device of claim 10 wherein the base semiconductor monolayers comprise silicon.
14. The vertical semiconductor device of claim 10 wherein the at least one non-semiconductor monolayer comprises oxygen.
15. The vertical semiconductor device of claim 10 wherein the superlattice liner also covers bottom portions of the at least one trench.
16. The vertical semiconductor device of claim 10 wherein the at least one trench comprises a plurality of trenches.
17. A vertical semiconductor device comprising:
a semiconductor substrate having at least one trench therein;
a superlattice liner at least partially covering sidewall portions of the at least one trench and defining a gap between opposing sidewall portions of the superlattice liner, the superlattice liner comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer, with each at least one oxygen monolayer of each group of layers being constrained within a crystal lattice of adjacent base silicon portions;
a semiconductor layer on the superlattice liner and comprising a dopant constrained therein by the superlattice liner; and
a conductive body within the at least one trench defining a source contact.
18. The vertical semiconductor device of claim 17 wherein the conductive body comprises a metal liner adjacent the semiconductor layer and comprising a first metal, and a metal body adjacent the metal liner, filling the at least one trench and comprising a second metal.
19. The vertical semiconductor device of claim 18 wherein the conductive body comprises silicide.
20. The vertical semiconductor device of claim 18 wherein the semiconductor layer comprises silicon; and the first metal comprises at least one of titanium, cobalt and nickel.
21. The vertical semiconductor device of claim 18 wherein the second metal comprises tungsten.
22. The vertical semiconductor device of claim 17 wherein the superlattice liner also covers bottom portions of the at least one trench.
23. The vertical semiconductor device of claim 17 wherein the at least one trench comprises a plurality of trenches.
24. A vertical semiconductor device comprising:
a semiconductor substrate having at least one trench therein;
a superlattice liner at least partially covering sidewall portions of the at least one trench, the superlattice liner comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer, with each at least one non-semiconductor monolayer of each group of layers being constrained within a crystal lattice of adjacent base semiconductor portions;
a semiconductor layer on the superlattice liner and comprising a dopant constrained therein by the superlattice liner; and
a conductive body within the at least one trench defining a source contact and comprising a metal liner adjacent the semiconductor layer and comprising a first metal, and a metal body adjacent the metal liner, filling the at least one trench and comprising a second metal.
25. The vertical semiconductor device of claim 24 wherein the conductive body comprises silicide.
26. The vertical semiconductor device of claim 24 wherein the at least one trench comprises a plurality of trenches.
27. A method for making a vertical semiconductor device comprising:
forming at least one trench in a semiconductor substrate;
forming a superlattice liner at least partially covering sidewall portions of the at least one trench and defining a gap between opposing sidewall portions of the superlattice liner, the superlattice liner comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer, with each at least one non-semiconductor monolayer of each group of layers being constrained within a crystal lattice of adjacent base semiconductor portions;
forming a semiconductor layer on the superlattice liner and comprising a dopant constrained therein by the superlattice liner; and
forming a conductive body within the at least one trench defining a source contact.
28. The method of claim 27 wherein the conductive body comprises a metal liner adjacent the semiconductor layer and comprising a first metal, and a metal body adjacent the metal liner, filling the at least one trench and comprising a second metal.
29. The method of claim 27 wherein the conductive body comprises silicide.
30. The method of claim 28 wherein the semiconductor layer comprises silicon; and the first metal comprises at least one of titanium, cobalt and nickel.
31. The method of claim 28 wherein the second metal comprises tungsten.
32. The method of claim 27 wherein the base semiconductor monolayers comprise silicon.
33. The method of claim 27 wherein the at least one non-semiconductor monolayer comprises oxygen.
34. The method of claim 27 wherein the superlattice liner also covers bottom portions of the at least one trench.
35. The method of claim 27 wherein the at least one trench comprises a plurality of trenches.