Method for making a radio frequency silicon-on-insulator (RFSOI) wafer including a superlattice
A method for making a semiconductor device may include, in an epitaxial deposition tool, performing an anneal on a semiconductor on insulator (SOI) substrate including a first semiconductor layer, an insulating layer on the first semiconductor layer, and a second semiconductor layer on the insulating layer, the second semiconductor layer having a first thickness. The method may also include, in the epitaxial deposition tool, performing an in-situ etch to reduce the second semiconductor layer to a second thickness less than the first thickness, and forming a superlattice layer on the second semiconductor layer. The superlattice layer may include a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
1. A method for making a semiconductor device comprising:
in an epitaxial deposition tool,
performing an anneal on a semiconductor on insulator (SOI) substrate comprising a first semiconductor layer, an insulating layer on the first semiconductor layer, and a second semiconductor layer on the insulating layer, the second semiconductor layer having a first thickness,
performing an in-situ etch at a temperature in a range of 950° C. to 1050° C. to reduce the second semiconductor layer to a second thickness less than the first thickness and with a haze in a range of 0.235 to 0.5 PPM, and
forming a superlattice layer on the second semiconductor layer, the superlattice layer comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
2. The method of claim 1 wherein the first thickness is in a range of 30 nm to 90 nm.
3. The method of claim 1 wherein the second thickness is in a range of 10 nm to 20 nm.
4. The method of claim 1 wherein performing the anneal comprises annealing the SOI substrate at a temperature greater than 1000° C.
5. The method of claim 1 wherein performing the anneal comprises annealing the SOI substrate in a hydrogen environment.
6. The method of claim 1 wherein performing the in-situ etch comprises performing an in-situ HCl etch.
7. The method of claim 6 wherein performing the in-situ HCl etch comprises introducing an HCl gas flow in a range of 100-1000 sccm.
8. The method of claim 1 wherein performing the in-situ etch comprises performing the in-situ at an etch rate in a range of 5-200 nm per minute.
9. The method of claim 1 further comprising epitaxially forming a third semiconductor layer on the superlattice layer, and forming at least one semiconductor circuit in the third semiconductor layer.
10. The method of claim 1 wherein the base semiconductor monolayers comprise silicon.
11. The method of claim 1 wherein the non-semiconductor monolayers comprise oxygen.
12. A method for making a semiconductor device comprising:
in an epitaxial deposition tool,
performing an anneal on a semiconductor on insulator (SOI) substrate comprising a first semiconductor layer, an insulating layer on the first semiconductor layer, and a second semiconductor layer on the insulating layer, the second semiconductor layer having a first thickness,
performing an in-situ etch at a temperature in a range of 950° C. to 1050° C. to reduce the second semiconductor layer to a second thickness less than the first thickness and with a haze in a range of 0.235 to 0.5 PPM,
forming a superlattice layer on the second semiconductor layer, the superlattice layer comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions, and
epitaxially forming a third semiconductor layer on the superlattice layer; and
forming at least one semiconductor circuit in the third semiconductor layer.
13. The method of claim 12 wherein the first thickness is in a range of 30 nm to 90 nm.
14. The method of claim 12 wherein the second thickness is in a range of 10 nm to 20 nm.
15. The method of claim 12 wherein performing the anneal comprises annealing the SOI substrate at a temperature greater than 1000° C. in a hydrogen environment.
16. The method of claim 12 wherein performing the in-situ etch comprises performing an in-situ HCl etch.
17. The method of claim 16 wherein performing the in-situ HCl etch comprises introducing an HCl gas flow in a range of 100-1000 sccm.
18. The method of claim 12 wherein performing the in-situ etch comprises performing the in-situ etch at an etch rate in a range of 5-200 nm per minute.
19. The method of claim 12 further comprising forming a coating on the first semiconductor layer prior to performing the in-situ etch.