IP Library › Granted Patent US 11,682,712
Granted Patent B2
US 11,682,712 · App. 17/330,860 · Granted Jun 20, 2023

Method for making semiconductor device including superlattice with O18 enriched monolayers

Inventors: Marek Hytha (Brookline, MA); Nyles Wynn Cody (Tempe, AZ); Keith Doran Weeks (Chandler, AZ)
Assignee: ATOMERA INCORPORATED
H01L29/66431H01L29/152
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Quick Facts
Patent No.
US 11,682,712
App. No.
17/330,860
Granted
Jun 20, 2023
Kind
B2
Abstract

A method for making a semiconductor device may include forming a semiconductor layer, and forming a superlattice adjacent the semiconductor layer and including stacked groups of layers. Each group of layers may include stacked base semiconductor monolayers defining a base semiconductor portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one oxygen monolayer of a given group of layers may comprise an atomic percentage of 18 O greater than 10 percent.

Claims (33)

1. A method for making a semiconductor device comprising:

forming a semiconductor layer; and

forming a superlattice adjacent the semiconductor layer and comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base semiconductor portions;

the at least one oxygen monolayer of a given group of layers comprising an atomic percentage of 18 O greater than 10 percent.

2. The method of claim 1 wherein the at least one oxygen monolayer of the given group of layers comprises an atomic percentage of 18 O greater than 50 percent.

3. The method of claim 1 wherein the at least one oxygen monolayer of the given group of layers comprises an atomic percentage of 18 O greater than 90 percent.

4. The method of claim 1 wherein the at least one oxygen monolayer of the given group of layers further comprises 16 O.

5. The method of claim 1 wherein the at least one oxygen monolayer of each group of layers comprises an atomic percentage of 18 O greater than 10 percent.

6. The method of claim 1 further comprising forming source and drain regions on the semiconductor layer and defining a channel in the superlattice, and forming a gate above the superlattice.

7. The method of claim 1 wherein the superlattice divides the semiconductor layer into a first region and a second region, with the first region having a same conductivity type as the second region and a different dopant concentration than the second region.

8. The method of claim 1 further comprising forming a metal layer above the superlattice.

9. The method of claim 1 wherein the superlattice divides the semiconductor layer into a first region and a second region, with the first region having a different conductivity type than the second region.

10. The method of claim 1 wherein the base semiconductor layer comprises silicon.

11. A method for making a semiconductor device comprising:

forming a semiconductor layer; and

forming a superlattice adjacent the semiconductor layer and comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions;

the at least one oxygen monolayer of a given group of layers comprising an atomic percentage of 18 O greater than 50 percent.

12. The method of claim 11 wherein the at least one oxygen monolayer of the given group of layers comprises an atomic percentage of 18 O greater than 90 percent.

13. The method of claim 11 wherein the at least one oxygen monolayer of the given group of layers comprises 16 O.

14. The method of claim 11 wherein the at least one oxygen monolayer of each group of layers within the superlattice comprises an atomic percentage of 18 O greater than 50 percent.

15. The method of claim 11 further comprising forming source and drain regions on the semiconductor layer and defining a channel in the superlattice, and forming a gate above the superlattice.

16. The method of claim 11 wherein the superlattice divides the semiconductor layer into a first region and a second region, with the first region having a same conductivity type as the second region and a different dopant concentration than the second region.

17. The method of claim 11 further comprising forming a metal layer above the superlattice.

18. The method of claim 11 wherein the superlattice divides the semiconductor layer into a first region and a second region, with the first region having a different conductivity type than the second region.

19. A method for making a semiconductor device comprising:

forming a semiconductor layer; and

forming a superlattice adjacent the semiconductor layer and comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions;

each at least one oxygen monolayer constrained within the crystal lattice of adjacent base silicon portions comprising an atomic percentage of 18 O greater than 90 percent.

20. The method of claim 19 wherein each at least one oxygen monolayer comprises 16 O.

21. The method of claim 19 further comprising forming source and drain regions on the semiconductor layer and defining a channel in the superlattice, and forming a gate above the superlattice.

22. The method of claim 19 wherein the superlattice divides the semiconductor layer into a first region and a second region, with the first region having a same conductivity type as the second region and a different dopant concentration than the second region.

23. The method of claim 19 further comprising forming a metal layer above the superlattice.

24. The method of claim 19 wherein the superlattice divides the semiconductor layer into a first region and a second region, with the first region having a different conductivity type than the second region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 28, 2021
From: HYTHA, MAREK; CODY, NYLES WYNN; WEEKS, KEITH DORAN
To: ATOMERA INCORPORATED
Reel/Frame 056384/0187 →
Continuity (1)
Related Publication 20220384612A1 · Dec 1, 2022
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