Methods for making bipolar junction transistors including emitter-base and base-collector superlattices
A method for making a bipolar junction transistor (BJT) may include forming a first superlattice on a substrate defining a collector region therein. The first superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a base on the first superlattice, and forming a second superlattice on the base comprising a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include forming an emitter on the second superlattice.
1. A method for making a bipolar junction transistor (BJT) comprising:
forming a first superlattice on a substrate, the substrate defining a collector region therein, the first superlattice comprising a plurality of stacked groups of first layers, each group of first layers comprising a first plurality of stacked base semiconductor monolayers defining a first base semiconductor portion, and at least one first non- semiconductor monolayer constrained within a crystal lattice of adjacent first base semiconductor portions;
forming a base on the first superlattice;
forming a second superlattice on the base comprising a second plurality of stacked groups of second layers, each group of second layers comprising a plurality of stacked base semiconductor monolayers defining a second base semiconductor portion, and at least one second non-semiconductor monolayer constrained within a crystal lattice of adjacent second base semiconductor portions; and
forming an emitter on the second superlattice.
2. The method of claim 1 wherein the substrate further defines a sub-collector region below the collector region; and further comprising forming a third superlattice in the substrate between the sub-collector region and the collector region.
3. The method of claim 2 wherein the third superlattice comprises a third plurality of stacked groups of third layers, each group of third layers comprising a third plurality of stacked base semiconductor monolayers defining a third base semiconductor portion, and at least one third non-semiconductor monolayer constrained within a crystal lattice of adjacent third base semiconductor portions.
4. The method of claim 1 further comprising forming an emitter contact on an upper surface of the emitter.
5. The method of claim 1 further comprising forming a base contact on at least a portion of the base.
6. The method of claim 1 further comprising forming spaced apart isolation regions in the substrate.
7. The method of claim 1 wherein the emitter and the collector have a first conductivity type, and the base has a second conductivity type different than the first conductivity type.
8. The method of claim 1 wherein the respective base semiconductor monolayers of the first and second superlattices comprise silicon monolayers.
9. The method of claim 1 wherein the respective at least one non-semiconductor monolayer of the first and second superlattices comprises oxygen.
10. The method of claim 1 wherein the respective base semiconductor monolayers of the first and second superlattices comprise germanium.
11. The method of claim 1 wherein the respective at least one non-semiconductor monolayer of the first and second superlattices comprises at least one of oxygen, nitrogen, fluorine, carbon and carbon-oxygen.