Method for making an inverted T channel field effect transistor (ITFET) including a superlattice
A method for making a semiconductor device may include forming an inverted T channel on a substrate, with the inverted T channel comprising a superlattice. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming source and drain regions on opposing ends of the inverted T channel, and forming a gate overlying the inverted T channel between the source and drain.
1. A method for making a semiconductor device comprising:
forming a superlattice on a substrate, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;
etching the superlattice to form an inverted T channel;
forming source and drain regions on opposing ends of the inverted T channel; and
forming a gate overlying the inverted T channel between the source and drain regions.
2. The method of claim 1 wherein forming the inverted T channel further comprises:
etching the superlattice to define a fin therein;
forming sidewall spacers on opposite sides of the fin;
etching portions of the superlattice laterally outside of the sidewall spacers to define the inverted T channel; and
removing the sidewall spacers.
3. The method of claim 1 wherein the substrate comprises a semiconductor-on-insulator (SOI) substrate.
4. The method of claim 1 wherein forming the gate comprises forming a gate insulator overlying the inverted T channel, and forming a gate electrode overlying the gate insulator.
5. The method of claim 1 wherein the base semiconductor monolayers comprise silicon.
6. The method of claim 1 wherein each base semiconductor portion comprises a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors.
7. The method of claim 1 wherein the at least one non-semiconductor monolayer comprises oxygen.
8. The method of claim 1 wherein the at least one non-semiconductor monolayer comprises a non- semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.
9. The method of claim 1 wherein all of the base semiconductor portions are a same number of monolayers thick.
10. The method of claim 1 wherein at least some of the base semiconductor portions are a different number of monolayers thick.
11. A method for making a semiconductor device comprising:
forming a superlattice on a semiconductor-on-insulator (SOI) substrate, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;
etching the superlattice to form an inverted T channel;
forming source and drain regions on opposing ends of the inverted T channel; and
forming a gate overlying the inverted T channel between the source and drain regions by forming a gate insulator overlying the inverted T channel, and forming a gate electrode overlying the gate insulator.
12. The method of claim 11 wherein forming the inverted T channel further comprises:
etching the superlattice to define a fin therein;
forming sidewall spacers on opposite sides of the fin;
etching portions of the superlattice laterally outside of the sidewall spacers to define the inverted T channel; and
removing the sidewall spacers.
13. The method of claim 11 wherein the base semiconductor monolayers comprise silicon.
14. The method of claim 11 wherein each base semiconductor portion comprises a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors.
15. The method of claim 11 wherein the at least one non-semiconductor monolayer comprises oxygen.
16. The method of claim 11 wherein the at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.
17. The method of claim 11 wherein all of the base semiconductor portions are a same number of monolayers thick.
18. The method of claim 11 wherein at least some of the base semiconductor portions are a different number of monolayers thick.
19. A method for making a semiconductor device comprising:
forming a superlattice on a substrate, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions;
etching the superlattice to form an inverted T channel;
forming source and drain regions on opposing ends of the inverted T channel; and
forming a gate overlying the inverted T channel between the source and drain regions.
20. The method of claim 19 wherein forming the inverted T channel further comprises:
etching the superlattice to define a fin therein;
forming sidewall spacers on opposite sides of the fin;
etching portions of the superlattice laterally outside of the sidewall spacers to define the inverted T channel; and
removing the sidewall spacers.
21. The method of claim 19 wherein the substrate comprises a semiconductor-on-insulator (SOI) substrate.
22. The method of claim 19 wherein forming the gate comprises forming a gate insulator overlying the inverted T channel, and forming a gate electrode overlying the gate insulator.
23. The method of claim 19 wherein all of the base semiconductor portions are a same number of monolayers thick.
24. The method of claim 19 wherein at least some of the base semiconductor portions are a different number of monolayers thick.