Semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance
A semiconductor device may include a semiconductor layer, spaced apart source and drain regions in the semiconductor layer with a channel region extending therebetween, and at least one dopant diffusion blocking superlattice dividing at least one of the source and drain regions into a lower region and an upper region with the upper region having a same conductivity and higher dopant concentration than the lower region. The at least one dopant diffusion blocking superlattice comprising a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a gate on the channel region.
1. A semiconductor device comprising:
a semiconductor layer;
spaced apart source and drain regions in the semiconductor layer with a channel region extending therebetween;
at least one dopant diffusion blocking superlattice dividing at least one of the source and drain regions into a lower region and an upper region with the upper region having a same conductivity and higher dopant concentration than the lower region;
the at least one dopant diffusion blocking superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; and
a gate on the channel region.
2. The semiconductor device of claim 1 wherein the at least one dopant diffusion blocking superlattice comprises a respective dopant diffusion blocking superlattice for each of the source and drain regions.
3. The semiconductor device of claim 1 further comprising a body dopant diffusion blocking superlattice in the semiconductor layer extending between the source and drain regions and comprising a respective plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
4. The semiconductor device of claim 1 wherein the upper region is level with an upper surface of the semiconductor layer.
5. The semiconductor device of claim 1 wherein the upper region is raised above an upper surface of the semiconductor layer.
6. The semiconductor device of claim 1 wherein the lower region comprises a different material than the upper region.
7. The semiconductor device of claim 1 further comprising a metal contact on the upper region.
8. The semiconductor device of claim 1 wherein the base semiconductor monolayers comprise silicon.
9. The semiconductor device of claim 1 wherein the at least one non-semiconductor monolayer comprises oxygen.
10. The semiconductor device of claim 6 wherein the lower region comprises silicon and the upper region comprises silicon germanium.
11. The semiconductor device of claim 6 wherein the lower region comprises silicon germanium and the upper region comprises silicon.
12. The semiconductor device of claim 7 wherein the metal contact comprises at least one of titanium, cobalt, nickel and platinum.
13. A semiconductor device comprising:
a semiconductor layer;
spaced apart source and drain regions in the semiconductor layer with a channel region extending therebetween;
a source dopant diffusion blocking superlattice extending through the source region to divide the source region into a lower source region and an upper source region with the upper source region having a same conductivity and higher dopant concentration than the lower source region;
a drain dopant diffusion blocking superlattice extending through the drain region to divide the drain region into a lower drain region and an upper drain region with the upper drain region having a same conductivity and higher dopant concentration than the lower drain region;
each of the source dopant diffusion blocking superlattice and drain dopant diffusion blocking superlattice, comprising a respective plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; and
a gate on the channel region;
wherein the upper drain region and upper source region are each level with an upper surface of the semiconductor layer.
14. The semiconductor device of claim 13 wherein the base semiconductor monolayers comprise silicon.
15. The semiconductor device of claim 13 wherein the at least one non-semiconductor monolayer comprises oxygen.
16. A semiconductor device comprising:
a semiconductor layer;
spaced apart source and drain regions in the semiconductor layer with a channel region extending therebetween;
a source dopant diffusion blocking superlattice extending through the source region to divide the source region into a lower source region and an upper source region with the upper source region having a same conductivity and higher dopant concentration than the lower source region;
a drain dopant diffusion blocking superlattice extending through the drain region to divide the drain region into a lower drain region and an upper drain region with the upper drain region having a same conductivity and higher dopant concentration than the lower drain region;
each of the source dopant diffusion blocking superlattice and drain dopant diffusion blocking superlattice comprising a respective plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; and
a gate on the channel region;
wherein the upper drain region and upper source region are each raised above an upper surface of the semiconductor layer.
17. The semiconductor device of claim 16 wherein the lower drain region comprises a different material than the upper drain region; and the lower source region comprises a different material than the upper source region.
18. The semiconductor device of claim 16 further comprising a metal source contact on the upper source region, and a metal drain contact on the upper drain region.
19. The semiconductor device of claim 17 wherein the lower source and drain regions comprise silicon; and wherein the upper source and drain regions comprise silicon germanium.
20. The semiconductor device of claim 17 wherein the lower source and drain regions comprise silicon germanium; and wherein the upper source and drain regions comprise silicon.
21. The semiconductor device of claim 18 wherein the metal source and drain contacts comprise at least one of titanium, cobalt, nickel and platinum.