IP Library Granted Patent US 11,355,667
Granted Patent B2
US 11,355,667 · App. 16/380,091 · Granted Jun 7, 2022

Method for making semiconductor device including vertically integrated optical and electronic devices and comprising a superlattice

Inventor: Robert John Stephenson (Duxford, GB)
Assignee: ATOMERA INCORPORATED
H01L33/06G02B6/12004G02B6/134G02F1/01708H01L21/02507H01L23/5226H01L27/1207H01L27/15H01L29/152H01L33/0054H01L33/34H01L33/58G02B6/12G02B2006/12061G02B2006/12142G02F1/01766H01L31/035236H01L33/04H01L2933/0058
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,355,667
App. No.
16/380,091
Granted
Jun 7, 2022
Kind
B2
Abstract

A method for making a semiconductor device may include forming a plurality of waveguides on a substrate, and forming a superlattice overlying the substrate and waveguides. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming an active device layer on the superlattice comprising at least one active semiconductor device.

Claims (33)

1. A method for making a semiconductor device comprising:

forming a plurality of waveguides on a substrate;

forming a superlattice overlying the substrate and waveguides, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; and

forming an active device layer on the superlattice comprising at least one active semiconductor device.

2. The method of claim 1 wherein the substrate comprises a semiconductor-on-insulator (SOI) substrate.

3. The method of claim 1 further comprising forming a plurality of optical modulator regions within the superlattice.

4. The method of claim 3 further comprising forming vias extending through the active device layer to the optical modulator regions.

5. The method of claim 3 further comprising planarizing the superlattice layer after forming the optical modulator regions.

6. The method of claim 3 wherein forming the optical modulator regions comprises implanting a dopant to define the optical modulator regions.

7. The method of claim 1 wherein the at least one active semiconductor device comprises at least one metal oxide semiconductor field effect transistor (MOSFET).

8. The method of claim 1 wherein the base semiconductor monolayers comprise silicon.

9. The method of claim 1 wherein the at least one non-semiconductor monolayer comprises oxygen.

10. A method for making a semiconductor device comprising:

forming a plurality of waveguides on a semiconductor-on-insulator (SOI) substrate;

forming a superlattice overlying the SOI substrate and waveguides, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;

forming a plurality of optical modulator regions within the superlattice; and

forming an active device layer on the superlattice comprising at least one active semiconductor device.

11. The method of claim 10 further comprising forming vias extending through the active device layer to the optical modulator regions.

12. The method of claim 10 further comprising planarizing the superlattice layer after forming the optical modulator regions.

13. The method of claim 10 wherein forming the optical modulator regions comprises implanting a dopant to define the optical modulator regions.

14. The method of claim 10 wherein the at least one active semiconductor device comprises at least one metal oxide semiconductor field effect transistor (MOSFET).

15. The method of claim 10 wherein the base semiconductor monolayers comprise silicon.

16. The method of claim 10 wherein the at least one non-semiconductor monolayer comprises oxygen.

17. A method for making a semiconductor device comprising:

forming a plurality of waveguides on a substrate;

forming a superlattice overlying the substrate and waveguides, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions; and

forming an active device layer on the superlattice comprising at least one active semiconductor device.

18. The method of claim 17 wherein the substrate comprises a semiconductor-on-insulator (SOI) substrate.

19. The method of claim 17 further comprising forming a plurality of optical modulator regions within the superlattice.

20. The method of claim 19 further comprising forming vias extending through the active device layer to the optical modulator regions.

21. The method of claim 19 further comprising planarizing the superlattice layer after forming the optical modulator regions.

22. The method of claim 19 wherein forming the optical modulator regions comprises implanting a dopant to define the optical modulator regions.

23. The method of claim 17 wherein the at least one active semiconductor device comprises at least one metal oxide semiconductor field effect transistor (MOSFET).

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 17, 2019
From: STEPHENSON, ROBERT JOHN
To: ATOMERA INCORPORATED
Reel/Frame 048909/0096 →
Continuity (2)
Provisional Application 62656469 · Apr 12, 2018
Related Publication 20190319167A1 · Oct 17, 2019
Cited By (11)
US 12,230,694 US 12,267,996 US 12,308,229 US 12,315,722 US 12,382,689 US 12,439,658 US 12,575,199 US 12,635,122 US 12,635,271 US 12,707,690 US 12,712,011