Varactor with hyper-abrupt junction region including spaced-apart superlattices
A semiconductor device may include a substrate and a hyper-abrupt junction region carried by the substrate. The hyper-abrupt junction region may include a first semiconductor layer having a first conductivity type, a first superlattice layer on the first semiconductor layer, a second semiconductor layer on the first superlattice layer and having a second conductivity type different than the first conductivity type, and a second superlattice layer on the second semiconductor layer. The semiconductor device may further include a first contact coupled to the hyper-abrupt junction regions and a second contact coupled to the substrate to define a varactor. The first and second superlattices may each include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
1. A semiconductor device comprising:
a substrate;
a hyper-abrupt junction region carried by the substrate and comprising
a first semiconductor layer having a first conductivity type,
a first superlattice layer on the first semiconductor layer,
a second semiconductor layer on the first superlattice layer and having a second conductivity type different than the first conductivity type, and
a second superlattice layer on the second semiconductor layer; and
a first contact coupled to the hyper-abrupt junction region and a second contact coupled to the substrate to define a varactor;
the first and second superlattices each comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
2. The semiconductor device of claim 1 wherein the first and second semiconductor layers and the first and second superlattice layers are parallel to underlying portions of the substrate.
3. The semiconductor device of claim 1 wherein the first contact layer comprises an epitaxial semiconductor region on the second superlattice layer.
4. The semiconductor device of claim 1 further comprising an intermediate semiconductor layer between the substrate and the hyper-abrupt junction; and wherein the second contact comprises an implant laterally spaced apart from the hyper-abrupt junction and extending from a surface of the intermediate semiconductor layer to the substrate.
5. The semiconductor device of claim 4 further comprising a collector implant in the intermediate semiconductor layer below the hyper-abrupt junction.
6. The semiconductor device of claim 1 wherein the first and second semiconductor layers each have a thickness in a range of 50 nm to 300 nm.
7. The semiconductor device of claim 1 wherein the base semiconductor monolayers comprise silicon monolayers.
8. The semiconductor device of claim 1 wherein the at least one non-semiconductor monolayer comprises oxygen.
9. The semiconductor device of claim 1 wherein the base semiconductor monolayers comprise germanium.
10. The semiconductor device of claim 1 wherein the at least one non-semiconductor monolayer comprises at least one of oxygen, nitrogen, fluorine, carbon and carbon-oxygen.
11. A semiconductor device comprising:
a substrate;
a hyper-abrupt junction region carried by the substrate and comprising
a first semiconductor layer having a first conductivity type,
a first superlattice layer on the first semiconductor layer,
a second semiconductor layer on the first superlattice layer and having a second conductivity type different than the first conductivity type, and
a second superlattice layer on the second semiconductor layer;
an intermediate semiconductor layer between the substrate and the hyper-abrupt junction; and
a first contact coupled to the hyper-abrupt junction region and a second contact coupled to the substrate to define a varactor;
the first contact comprising an epitaxial semiconductor region on the second superlattice layer, and the second contact comprising an implant laterally spaced apart from the hyper-abrupt junction and extending from a surface of the intermediate semiconductor layer to the substrate;
the first and second superlattices each comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
12. The semiconductor device of claim 11 wherein the first and second semiconductor layers and the first and second superlattice layers are parallel to underlying portions of the substrate.
13. The semiconductor device of claim 11 further comprising a collector implant in the intermediate semiconductor layer below the hyper-abrupt junction.
14. The semiconductor device of claim 11 wherein the first and second semiconductor layers each have a thickness in a range of 50 nm to 300 nm.
15. The semiconductor device of claim 11 wherein the base semiconductor monolayers comprise silicon monolayers.
16. The semiconductor device of claim 11 wherein the at least one non-semiconductor monolayer comprises oxygen.
17. A semiconductor device comprising:
a substrate;
a hyper-abrupt junction region carried by the substrate and comprising
a first semiconductor layer having a first conductivity type,
a first superlattice layer on the first semiconductor layer,
a second semiconductor layer on the first superlattice layer and having a second conductivity type different than the first conductivity type, and
a second superlattice layer on the second semiconductor layer; and
a first contact coupled to the hyper-abrupt junction region and a second contact coupled to the substrate to define a varactor;
the first and second superlattices each comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions.
18. The semiconductor device of claim 17 wherein the first and second semiconductor layers and the first and second superlattice layers are parallel to underlying portions of the substrate.
19. The semiconductor device of claim 17 wherein the first contact layer comprises an epitaxial semiconductor region on the second superlattice layer.
20. The semiconductor device of claim 17 further comprising an intermediate semiconductor layer between the substrate and the hyper-abrupt junction; and wherein the second contact comprises an implant laterally spaced apart from the hyper-abrupt junction and extending from a surface of the intermediate semiconductor layer to the substrate.
21. The semiconductor device of claim 20 further comprising a collector implant in the intermediate semiconductor layer below the hyper-abrupt junction.
22. The semiconductor device of claim 17 wherein the first and second semiconductor layers each have a thickness in a range of 50 nm to 300 nm.