Semiconductor device and method for manufacturing the same

1. A semiconductor device, comprising:

at least one n-channel;

at least one p-channel;

at least one first high-k dielectric sheath surrounding the n-channel;

at least one second high-k dielectric sheath surrounding the p-channel, the first high-k dielectric sheath and the second high-k dielectric sheath comprising different high-k dielectric materials;

a first metal gate electrode surrounding and in contact with the first high-k dielectric sheath; and

a second metal gate electrode surrounding and in contact with the second high-k dielectric sheath, wherein the first and second metal gate electrodes are made of the same material.

2. The semiconductor device of claim 1 , wherein the first metal gate electrode and the second metal gate electrode are made of a single metal.

3. The semiconductor device of claim 1 , wherein the first high-k dielectric sheath comprises Y 2 O 3 , Lu 2 O 3 , La 2 O 3 , SrO, Er, Sc, or combinations thereof.

4. The semiconductor device of claim 1 , wherein the second high-k dielectric sheath comprises Al 2 O 3 , TiO 2 , ZrO 2 , MgO, or combinations thereof.

5. The semiconductor device of claim 1 , wherein the first high-k dielectric sheath is made of La 2 O 3 , and the second high-k dielectric sheath is made of Al 2 O 3 .

6. The semiconductor device of claim 1 , further comprising:

a first high-k dielectric lining on an inner surface of the first high-k dielectric sheath; and

a second high-k dielectric lining on an inner surface of the second high-k dielectric sheath, the first high-k dielectric lining and the second high-k dielectric lining comprising the same material.

7. The semiconductor device of claim 6 , wherein the first high-k dielectric lining is in contact with the inner surface of the first high-k dielectric sheath.

8. The semiconductor device of claim 7 , wherein the second high-k dielectric lining is in contact with the inner surface of the second high-k dielectric sheath.

9. The semiconductor device of claim 1 , wherein a plurality of the at least one first high-k dielectric sheaths respectively surround a plurality of the at least one n-channels, and the first high-k dielectric sheaths are separated from each other, wherein a plurality of the at least one second high-k dielectric sheaths respectively surround a plurality of the at least one p-channels, and the second high-k dielectric sheaths are separated from each other.

10. The semiconductor device of claim 1 , wherein a plurality of the at least one first high-k dielectric sheaths respectively surround a plurality of the at least one n-channels, and the first high-k dielectric sheaths are merged, wherein a plurality of the at least one second high-k dielectric sheaths respectively surround a plurality of the at least one p-channels, and the second high-k dielectric sheaths are merged.

11. The semiconductor device of claim 1 , wherein the first and second metal gate electrodes are integral with each other.

12. A semiconductor device, comprising:

a substrate;

a first gate-all-around (GAA) transistor on the substrate, the first GAA transistor comprising a first high-k dielectric sheath and a first metal gate electrode around and in contact with the first high-k dielectric sheath, wherein the first metal gate electrode is formed from a metal layer; and

a second GAA transistor on the substrate, the second GAA transistor comprising a second high-k dielectric sheath and a second metal gate electrode around and in contact with the second high-k dielectric sheath, wherein the second metal gate electrode is formed from the same metal layer as the first metal gate electrode.

13. The semiconductor device of claim 12 , wherein the first high-k dielectric sheath and the second high-k dielectric sheath are made of different materials.

14. The semiconductor device of claim 12 , wherein the first GAA further comprises a first high-k dielectric lining, and the first high-k dielectric sheath is between the first high-k dielectric lining and the first metal gate electrode.

15. The semiconductor device of claim 14 , wherein the second GAA further comprises a second high-k dielectric lining, and the second high-k dielectric sheath is between the second high-k dielectric lining and the second metal gate electrode.

16. The semiconductor device of claim 15 , wherein the first high-k dielectric lining and the second high-k dielectric lining are made of the same material.

17. The semiconductor device of claim 12 , wherein the first GAA transistor is an n-type transistor, and the second GAA transistor is a p-type transistor.

18. A method of forming a semiconductor device, comprising:

forming at least one first nanowire over a substrate;

forming a second nanowire over the substrate;

forming at least one first high-k dielectric sheath around the first nanowire;

forming a second high-k dielectric sheath around the second nanowire, wherein the first high-k dielectric sheath and the second high-k dielectric sheath are made of different materials; and

forming a single metal layer around and in contact with the first high-k dielectric sheath and the second high-k dielectric sheath.

19. The method of claim 18 , wherein the forming the metal layer comprises filling a space between the first high-k dielectric sheath and the second high-k dielectric sheath with a single metal.

20. The method of claim 18 , wherein the forming the at least one first high-k dielectric sheath comprises forming a plurality of the at least one first high-k dielectric sheaths respectively around a plurality of the at least one first nanowires until the first high-k dielectric sheaths are merged.