Techniques for read operations
Methods, systems, devices, and techniques for read operations are described. In some examples, a memory device may include a first transistor (e.g., memory node transistor) configured to receive a precharge voltage at a first gate and output first voltage based on a threshold of the first transistor to a reference node via a first switch. The device may include a second transistor (e.g., a reference node transistor) configured to receive a precharge voltage and output a second voltage based on a threshold of the second transistor to a memory node via a second switch. The first voltage may be modified by a reference voltage and input to the second transistor. The second voltage may be modified by a voltage stored on a memory cell and input to the first transistor. The first and second transistor may output third and fourth voltages to be sampled to a latch.
1. A method, comprising:
coupling a first node to a first voltage source to increase the first node to a first voltage level as part of a read operation of a memory cell;
coupling a second node to a second voltage source to increase the second node to a second voltage level as part of the read operation of the memory cell;
applying a voltage increase to a first capacitor coupled with the first node to increase a third voltage level of the first node based at least in part on coupling the first node to the first voltage source;
coupling the first node with the second node based at least in part on applying the voltage increase to the first capacitor; and
applying a reference voltage to a latch during the read operation based at least in part on coupling the first node to the second node.
2. The method of claim 1 , further comprising:
isolating the second node from the second voltage source by deactivating a first transistor before coupling the first node to the second node.
3. The method of claim 1 , further comprising:
coupling the second node to a fourth voltage source by activating a second transistor before coupling the first node to the second node.
4. The method of claim 1 , further comprising:
precharging a second capacitor coupled with the second node based at least in part on the third voltage level associated with a digit line coupled with the first node.
5. The method of claim 1 , further comprising:
coupling, as part of the read operation, a third node associated with the memory cell to a third voltage source to increase the third voltage level of the third node; and
coupling the third node to a digit line to increase a fourth voltage level of the digit line.
6. The method of claim 5 , further comprising:
applying the voltage increase to a third capacitor coupled with the third node based at least in part on coupling the third node to the digit line.
7. The method of claim 6 , further comprising:
applying a fifth voltage indicating a logic state stored on the memory cell to the latch during the read operation based at least in part applying the voltage increase to the first capacitor and the third capacitor.
8. The method of claim 7 , further comprising:
determining the logic state stored on the memory cell based at least in part on comparing the fifth voltage to the reference voltage.
9. An apparatus, comprising:
a memory device;
a controller coupled with the memory device and configured to cause the apparatus to:
couple a first node to a first voltage source to increase the first node to a first voltage level as part of a read operation of a memory cell;
couple a second node to a second voltage source to increase the second node to a second voltage level as part of the read operation of the memory cell;
apply a voltage increase to a first capacitor coupled with the first node to increase a third voltage level of the first node based at least in part on coupling the first node to the first voltage source;
couple the first node with the second node based at least in part on applying the voltage increase to the first capacitor; and
apply a reference voltage to a latch during the read operation based at least in part on coupling the first node to the second node.
10. The apparatus of claim 9 , wherein the controller is further configured to cause the apparatus to:
isolate the second node from the second voltage source by deactivating a first transistor before coupling the first node to the second node.
11. The apparatus of claim 9 , wherein the controller is further configured to cause the apparatus to:
couple the second node to a fourth voltage source by activating a second transistor before coupling the first node to the second node.
12. The apparatus of claim 9 , wherein the controller is further configured to cause the apparatus to:
precharge a second capacitor coupled with the second node based at least in part on the third voltage level associated with a digit line coupled with the first node.
13. The apparatus of claim 9 , wherein the controller is further configured to cause the apparatus to:
couple, as part of the read operation, a third node associated with the memory cell to a third voltage source to increase the third voltage level of the third node; and
couple the third node to a digit line to increase a fourth voltage level of the digit line.
14. The apparatus of claim 13 , wherein the controller is further configured to cause the apparatus to:
apply the voltage increase to a third capacitor coupled with the third node based at least in part on coupling the third node to the digit line.
15. The apparatus of claim 14 , wherein the controller is further configured to cause the apparatus to:
apply a fifth voltage indicating a logic state stored on the memory cell to the latch during the read operation based at least in part applying the voltage increase to the first capacitor and the third capacitor.
16. The apparatus of claim 15 , wherein the controller is further configured to cause the apparatus to:
determine the logic state stored on the memory cell based at least in part on comparing the fifth voltage to the reference voltage.