Bonded memory devices and methods of making the same
At least a portion of a memory cell is formed over a first substrate and at least a portion of a steering element or word or bit line of the memory cell is formed over a second substrate. The at least a portion of the memory cell is bonded to at least a portion of a steering element or word or bit line. At least one of the first or second substrate may be removed after the bonding.
1. A memory device, comprising:
a first electrically conductive line laterally extending along a first horizontal direction;
a memory pillar structure overlying and contacting the first electrically conductive line, wherein the memory pillar structure comprises, from bottom to top:
a stack of a first metallic material plate consisting essentially of a first elemental metal and a second metallic material plate consisting essentially of a second elemental metal and bonded to the first metallic material plate at a bonding interface;
a single crystalline ferroelectric material plate comprising a ferroelectric dielectric metal oxide material having a first single crystalline crystal structure, and
a single crystalline semiconductor plate comprising a semiconductor material having a second single crystalline crystal structure, wherein the second single crystalline crystal structure of the semiconductor material is in epitaxial alignment with the first single crystalline crystal structure of the ferroelectric dielectric metal oxide material at an interface between the semiconductor material and the ferroelectric dielectric metal oxide material; and
a second electrically conductive line laterally extending along a second horizontal direction and overlying and contacting the memory pillar structure.
2. The memory device of claim 1 , wherein:
the memory pillar structure further comprises a selector material plate underlying the first metallic material plate; and
the bonding interface is located between the selector material plate and the single crystalline ferroelectric material plate.
3. The memory device of claim 2 , further comprising:
a lower electrode plate contacting a bottom surface of the selector material plate and comprising a first non-metallic conductive material; and
an upper electrode plate contacting a top surface of the selector material plate and comprising a second non-metallic conductive material.
4. The memory device of claim 3 , wherein:
the selector material plate comprises an ovonic threshold switch material; and
each of the first non-metallic conductive material and the second non-metallic conductive material is selected from amorphous carbon, amorphous boron-doped carbon, amorphous nitrogen-doped carbon, amorphous silicon, amorphous germanium, alloys thereof, or layer stacks thereof.
5. The memory device of claim 1 , wherein the second metallic material plate contacts a bottom surface of the first metallic material plate.
6. The memory device of claim 5 , wherein the second metallic material plate is not in direct contact with the first electrically conductive line.
7. The memory device of claim 1 , wherein the ferroelectric material of the single crystalline ferroelectric material plate comprises doped or undoped hafnium oxide having an orthorhombic phase.
8. The memory device of claim 1 , wherein the single crystalline semiconductor plate contacts an entirety of a top surface of the single crystalline ferroelectric material plate.
9. The memory device of claim 1 , wherein the single crystalline semiconductor plate comprises single crystalline germanium or silicon germanium.
10. The memory device of claim 1 , wherein the memory pillar structure comprises a metallic cap plate overlying the single crystalline ferroelectric material plate and contacting the second electrically conductive line.
11. The memory device of claim 1 , wherein the memory pillar structure further comprises a selector material plate.
12. The memory device of claim 11 , wherein the selector material plate comprises an ovonic threshold switch material.
13. The memory device of claim 1 , wherein the memory pillar structure comprises straight sidewalls each vertically extending from the first electrically conductive line to the second electrically conductive line.
14. The memory device of claim 1 , further comprising a dielectric isolation structure laterally surrounding and contacting the memory pillar structure.