Memory device
A memory device includes a bottom electrode, an MTJ stack, and a top electrode. The bottom electrode has a lower sidewall and an upper sidewall above the lower sidewall and laterally set back from the lower sidewall. The MTJ stack is over the bottom electrode. The MTJ stack includes a bottom magnetic layer, a tunnel barrier layer over the bottom magnetic layer and a top magnetic layer over the tunnel barrier layer. The bottom magnetic layer has a sidewall coterminous with the upper sidewall of the bottom electrode. The top magnetic layer has a sidewall laterally set back from the upper sidewall of the bottom electrode. The top electrode is over the MTJ stack.
1. A memory device, comprising:
a bottom electrode having a lower sidewall and an upper sidewall above the lower sidewall and laterally set back from the lower sidewall;
a magnetic tunnel junction (MTJ) stack over the bottom electrode, the MTJ stack comprising a bottom magnetic layer, a tunnel barrier layer over the bottom magnetic layer and a top magnetic layer over the tunnel barrier layer, wherein the bottom magnetic layer has a sidewall aligned with the upper sidewall of the bottom electrode, and the top magnetic layer has a sidewall laterally set back from the upper sidewall of the bottom electrode; and
a top electrode over the MTJ stack.
2. The memory device of claim 1 , further comprising:
a first spacer laterally surrounding the top magnetic layer and the top electrode, wherein an entirety of the first spacer is above the tunnel barrier layer.
3. The memory device of claim 2 , further comprising:
a second spacer laterally surrounding the first spacer, the tunnel barrier layer, the bottom magnetic layer and the upper sidewall of the bottom electrode, wherein an entirety of the second spacer is above the lower sidewall of the bottom electrode.
4. The memory device of claim 1 , wherein the top electrode has a width equal to a width of the top magnetic layer and less than a width of the tunnel barrier layer.
5. The memory device of claim 1 , wherein the bottom magnetic layer has a width equal to a width of the tunnel barrier layer and greater than a width of the top magnetic layer.
6. The memory device of claim 1 , further comprising:
a first metal residue on the sidewall of the top magnetic layer; and
a second metal residue on a sidewall of the bottom magnetic layer and separated from the first metal residue.
7. The memory device of claim 6 , wherein the first metal residue is further on a sidewall of the top electrode.
8. The memory device of claim 6 , wherein the second metal residue is further on the upper sidewall of the bottom electrode.
9. The memory device of claim 8 , wherein the second metal residue is spaced apart from the lower sidewall of the bottom electrode.
10. The memory device of claim 1 , wherein the sidewall of the top magnetic layer is misaligned with a sidewall of the tunnel barrier layer.
11. A memory device, comprising:
a bottom electrode having a lower sidewall and an upper sidewall above the lower sidewall and laterally set back from the lower sidewall;
a first spacer over the bottom electrode and having an outermost sidewall coterminous with the lower sidewall of the bottom electrode;
a magnetic tunnel junction (MTJ) stack laterally surrounded by the first spacer, the MTJ stack comprising a bottom magnetic layer, a tunnel barrier layer over the bottom magnetic layer and a top magnetic layer over the tunnel barrier layer, wherein the bottom magnetic layer is laterally spaced apart from the outermost sidewall of the first spacer by a first distance, and the top magnetic layer is laterally spaced apart from the outermost sidewall of the first spacer by a second distance greater than the first distance;
a top electrode laterally surrounded by the first spacer; and
a second spacer laterally surrounding the top electrode and laterally surrounded by the first spacer.
12. The memory device of claim 11 , wherein the tunnel barrier layer is laterally spaced apart from the outermost sidewall of the first spacer by a third distance less than the second distance.
13. The memory device of claim 12 , wherein the third distance is the same as the first distance.
14. The memory device of claim 11 , wherein the second spacer is entirely above the tunnel barrier layer.
15. The memory device of claim 11 , further comprising:
a metal residue encapsulated by the second spacer.
16. The memory device of claim 11 , further comprising:
a metal residue below the second spacer and encapsulated by the first spacer.
17. A memory device, comprising:
a bottom electrode having a lower sidewall and an upper sidewall above the lower sidewall and laterally set back from the lower sidewall;
a magnetic tunnel junction (MTJ) stack over the bottom electrode, the MTJ stack comprising a bottom magnetic layer, a tunnel barrier layer over the bottom magnetic layer and a top magnetic layer over the tunnel barrier layer, wherein the tunnel barrier layer has a sidewall substantially aligned with the upper sidewall of the bottom electrode, and the top magnetic layer has a sidewall laterally set back and misaligned from the sidewall of the tunnel barrier layer; and
a top electrode over the top magnetic layer.
18. The memory device of claim 17 , wherein the bottom magnetic layer has a sidewall laterally set back from the lower sidewall of the bottom electrode.
19. The memory device of claim 17 , further comprising:
a metal residue on the upper sidewall of the bottom electrode and absent from the lower sidewall of the bottom electrode.
20. The memory device of claim 17 , further comprising:
a metal residue on the sidewall of the top magnetic layer and absent from the sidewall of the tunnel barrier layer.