Transistor having stacked source/drain regions with formation assistance regions and multi-region wrap-around source/drain contacts
Embodiments of the invention are directed to a method of performing fabrication operations to form a transistor, wherein the fabrication operations include forming a source or drain (S/D) region having stacked, spaced-apart, and doped S/D layers. The fabrication operations further include forming a multi-region S/D contact structure configured to contact a top surface, a bottom surface, and sidewalls of each of the stacked, spaced-apart, and doped S/D layers.
1. A method of performing fabrication operations to form a transistor, wherein the fabrication operations include:
forming a source or drain (S/D) region comprising stacked, spaced-apart, and doped S/D layers; and
forming a multi-region S/D contact structure configured to contact a top surface, a bottom surface, and sidewalls of each of the stacked, spaced-apart, and doped S/D layers;
wherein the multi-region S/D contact structure comprises stacked and spaced-apart S/D contact layers.
2. The method of claim 1 , wherein:
forming the multi-region S/D contact structure comprises forming a sacrificial multi-region S/D contact structure; and
replacing the sacrificial multi-region S/D contact structure with the multi-region S/D contact structure.
3. The method of claim 1 , wherein the fabrication operations further include forming an S/D contact structure comprising an upper S/D contact structure communicatively coupled to the multi-region S/D contact structure.
4. The method of claim 1 , wherein the stacked, spaced-apart, and doped S/D layers and the stacked and spaced-apart S/D contact layers form a stack.
5. The method of claim 4 , wherein the multi-region S/D contact structure further comprises a high aspect-ratio leg region.
6. The method of claim 5 , wherein the high aspect-ratio leg region is communicatively coupled to sidewall surfaces of the stacked and spaced-apart S/D contact layers.
7. The method of claim 6 , wherein the high aspect-ratio leg region is communicatively coupled to sidewall surfaces of the stacked, spaced-apart, and doped S/D layers.
8. The method of claim 4 , wherein:
forming the multi-region S/D contact structure comprises forming the stack; and
forming the stack comprises forming a formation assistance region in a substrate of the transistor.
9. The method of claim 8 , wherein forming the stack further comprises:
epitaxially growing an initial portion of a sacrificial multi-region S/D contact structure from the formation assistance region;
epitaxially growing an initial portion of the multi-region S/D contact structure from the initial portion of the sacrificial multi-region S/D contact structure;
epitaxially growing subsequent portions of the sacrificial multi-region S/D contact; and
epitaxially growing subsequent portions of the multi-region S/D contact structure.
10. The method of claim 9 , wherein forming the stack further comprises replacing the sacrificial multi-region S/D contact structure with the multi-region S/D contact structure.
11. The method of claim 10 , wherein the formation assistance region is configured to provide electrical isolation of the stack from the substrate.
12. The method of claim 11 , wherein forming the formation assistance region comprises doping the formation assistance region such that the formation assistance region provides electrical isolation of the stack from the substrate.
13. A transistor device comprising:
a source or drain (S/D) region comprising stacked, spaced-apart, and doped S/D layers; and
a multi-region S/D contact structure configured to contact a top surface, a bottom surface, and sidewalls of each of the stacked, spaced-apart, and doped S/D layers;
wherein the multi-region S/D contact structure comprises stacked and spaced-apart S/D contact layers.
14. The device of claim 13 , wherein the S/D contact structure comprises an upper S/D contact structure communicatively coupled to the multi-region S/D contact structure.
15. The device of claim 13 , wherein the stacked, spaced-apart, and doped S/D layers and the stacked and spaced-apart S/D contact layers form a stack.
16. The device of claim 15 , wherein the multi-region S/D contact structure further comprises a high aspect-ratio leg region.
17. The device of claim 16 , wherein the high aspect-ratio leg region is communicatively coupled to sidewall surfaces of the stacked and spaced-apart S/D contact layers.
18. The device 16 further comprising a formation assistance region in a substrate of the transistor, wherein the formation assistance region is configured to provide electrical isolation of the stack from the substrate.
19. The device of claim 17 , wherein the high aspect-ratio leg region is communicatively coupled to sidewall surfaces of the stacked, spaced-apart, and doped S/D layers.