Stacked FET contact formation
Semiconductor devices and methods of making the same include a first lower device and a second lower device on a substrate. A first upper device is over the first lower device and a second upper device is over the second lower device. A first lower contact extends from a height above the first upper device and makes electrical contact with a top surface and a sidewall surface of the first lower device. A second lower contact extends from a height above the second upper device and makes electrical contact with a top surface and a sidewall surface of the second lower device. An insulating barrier is between the first lower contact and the second lower contact.
1. A semiconductor device, comprising:
a first lower device and a second lower device on a substrate;
a first upper device over the first lower device and a second upper device over the second lower device;
a first lower contact that extends from a height above the first upper device and makes electrical contact with a top surface and a sidewall surface of the first lower device and that extends laterally underneath the first upper device;
a second lower contact that extends from a height above the second upper device and makes electrical contact with a top surface and a sidewall surface of the second lower device and that extends laterally underneath the second upper device; and
an insulating barrier between the first lower contact and the second lower contact.
2. The semiconductor device of claim 1 , wherein the insulating barrier comprises a dielectric liner and a dielectric fill formed from distinct dielectric materials.
3. The semiconductor device of claim 2 , wherein the dielectric liner is formed from a high-k dielectric material and the dielectric fill is formed from silicon dioxide.
4. The semiconductor device of claim 1 , wherein the first lower contact has a width that is different from a width of the second lower contact.
5. The semiconductor device of claim 1 , wherein the substrate includes a shallow trench isolation (STI) region between the first lower device and the second lower device, and wherein the insulating barrier extends to a depth below a top surface of the STI region.
6. The semiconductor device of claim 1 , wherein a sidewall of the first lower contact in a portion that extends laterally underneath the first upper device is sloped.
7. The semiconductor device of claim 1 , wherein the first lower contact makes electrical contact with a source/drain portion of the first lower device and the second lower contact makes electrical contact with a source/drain portion of the second lower device.
8. The semiconductor device of claim 1 , further comprising a back-end-of-line (BEOL) layer that includes a first line in electrical contact with the first lower contact and a second line in electrical contact with the second lower contact.
9. The semiconductor device of claim 1 , wherein the first lower contact and the second lower contact lack voids.