Semiconductor device package and method of manufacturing the same
A semiconductor device package and a method for manufacturing the semiconductor device package are provided. The semiconductor device package includes a carrier, an electronic component, a first encapsulant and a conductive via. The carrier has a first surface and a second surface opposite to the first surface. The semiconductor device is mounted at the second surface of the carrier. The first encapsulant encapsulates the first surface of the carrier and has a surface facing away from the first surface of the carrier. The conductive via extends from the surface of the first encapsulant into the carrier.
1. A semiconductor device package, comprising:
a carrier having a first surface and a second surface opposite to the first surface;
a first electronic component disposed on the second surface of the carrier;
a first encapsulant encapsulating the first surface of the carrier and having a first surface facing away from the first surface of the carrier and a second surface facing the first surface of the carrier; and
a conductive via extending from the first surface of the first encapsulant into the carrier, wherein the conductive via comprises a first portion within the carrier and a second portion within the first encapsulant;
wherein the first portion of the conductive via has a first diameter adjacent to the first surface of the carrier and the second portion of the conductive via has a second diameter adjacent to the second surface of the first encapsulant, and wherein the first diameter is substantially equal to the second diameter;
wherein the conductive via comprises a first thermal via overlapping with the first electronic component from a bottom view perspective, and wherein a second thermal via extending from the first surface of the first encapsulant to the carrier and free from overlapping with the first electronic component from the bottom view perspective.
2. The semiconductor device package of claim 1 , wherein a diameter of the first portion of the conductive via is equal to a diameter of the second portion of the conductive via.
3. The semiconductor device package of claim 1 , wherein the conductive via electrically connects to the first electronic component.
4. The semiconductor device package of claim 1 , wherein the conductive via extends through the carrier.
5. The semiconductor device package of claim 4 , wherein the conductive via contacts a bonding wire and is configured to electrically connect to the first electronic component.
6. The semiconductor device package of claim 4 , wherein the conductive via contacts an adhesive layer and is configured to electrically connect to the first electronic component.
7. The semiconductor device package of claim 4 , wherein the conductive via contacts an electrical connection configured to electrically connect to the first electronic component.
8. The semiconductor device package of claim 4 , wherein the first electronic component comprises a number of the electrical connections and wherein at least one of the electrical connections contacts the conductive via.
9. The semiconductor device package of claim 1 , wherein the conductive via connects to an interconnection structure of the carrier.
10. The semiconductor device package of claim 1 , wherein the first electronic component overlaps the conductive via from a top view perspective.
11. The semiconductor device package of claim 1 , wherein the carrier comprises a fan-out circuit layer.
12. The semiconductor device package of claim 1 , further comprising a second encapsulant encapsulating the second surface of the carrier and the first electronic component.
13. A semiconductor device package, comprising:
a carrier having a first surface and a second surface opposite to the first surface;
an electronic component disposed on the second surface of the carrier;
a first encapsulant encapsulating the first surface of the carrier and having a surface facing away from the first surface of the carrier; and
a conductive via extending from the surface of the first encapsulant into the carrier;
wherein the conductive via has a plurality of conductive particles and at least one of the conductive particle crosses a boundary plane between the first encapsulant and the carrier.
14. The semiconductor device package of claim 13 , wherein the conductive via is formed by a mechanical process.
15. The semiconductor device package of claim 13 , wherein the conductive via extends to the second surface of the carrier.
16. The semiconductor device package of claim 13 , wherein the conductive via extends through the carrier.
17. The semiconductor device package of claim 16 , wherein the conductive via contacts an electrical connection and is configured to electrically connect to the electronic component.
18. The semiconductor device package of claim 1 , further comprising a second electronic component disposed on the first surface of the carrier and covered by the first encapsulant, wherein the second electronic component has a portion exposed from the first encapsulant.
19. The semiconductor device package of claim 9 , further comprising a shielding layer covering a side surface of the carrier and a side surface of the first encapsulant and electrically connecting the conductive via through the interconnection structure.