Chamfered die of semiconductor package and method for forming the same

1. A semiconductor device, comprising:

a first die, the first die comprising a chamfered corner and a seal ring, the seal ring of the first die being along the chamfered corner;

an encapsulant over a front-side surface of the first die, the encapsulant at least partially surrounding the first die;

a redistribution structure on the encapsulant;

a thermal interface material on a back-side surface of the first die, the back-side surface being opposite the front-side surface;

a thermal module thermally and physically coupled to the back-side surface of the first die with the thermal interface material; and

a bolt extending through the redistribution structure and the thermal module, the bolt being adjacent to the chamfered corner.

2. The semiconductor device of claim 1 , wherein the first die is an integrated circuit die.

3. The semiconductor device of claim 1 , wherein the first die is a dummy die.

4. The semiconductor device of claim 1 , wherein the first die comprises four chamfered corners.

5. The semiconductor device of claim 1 , wherein the first die has only one chamfered corner.

6. The semiconductor device of claim 1 , wherein the chamfered corner comprises a straight line shape.

7. The semiconductor device of claim 1 , wherein the chamfered corner comprises a concave shape.

8. The semiconductor device of claim 1 , wherein the chamfered corner comprises a convex shape.

9. The semiconductor device of claim 1 , wherein the chamfered corner comprises an inverted corner.

10. A packaged semiconductor device, comprising:

a first chamfered corner on a first die;

a second chamfered corner on a second die;

a third chamfered corner on a third die;

a fourth chamfered corner on a fourth die, the fourth die having a seal ring, wherein a portion of the seal ring is parallel to a top edge of the fourth chamfered corner;

an encapsulant encapsulating the first die, the second die, the third die, and the fourth die, the encapsulant covering the fourth chamfered corner;

a redistribution structure over the encapsulant, the first die, the second die, the third die, and the fourth die;

a thermal module thermally and physically coupled to the first die, the second die, the third die, and the fourth die, the thermal module being opposite the redistribution structure; and

a bolt extending through the redistribution structure, the bolt being surrounded by the first, second, third, and fourth chamfered corners, the bolt further extending through the thermal module.

11. The packaged semiconductor device of claim 10 , wherein the first die has a first length measured between opposite sidewalls, the first chamfered corner has a second length measured between the outer vertex of the first chamfered corner to a vertex of the first chamfered corner on a remaining sidewall of the first die, and the ratio of the second length to the first length is in a range of 0.01 to 0.3.

12. The packaged semiconductor device of claim 10 , wherein the first chamfered corner has a first surface area measured between the outer vertex of the first chamfered corner and vertices of the first chamfered corner on remaining sidewalls of the first die, the first die has an original surface area measured on the top surface of the first die before chamfering, and the ratio of the first surface area to the original surface area is in a range of 0.01 to 0.3.

13. The packaged semiconductor device of claim 10 , wherein an angle θ between a bottom of the first die and the chamfered face of the first chamfered corner is in a range of 30° to 90°.

14. A semiconductor device, comprising:

a thermal module;

a thermal interface material (TIM) on the thermal module; and

a package component on the TIM, the package component being secured to the thermal module by a plurality of bolts, each bolt of the plurality of bolts extending through the package component and the thermal module, wherein the package component comprises:

a plurality of dies, each die of the plurality of dies having at least one respective chamfered corner, wherein each bolt of the plurality of bolts is surrounded by corresponding ones of the chamfered corners, wherein a first die of the plurality of dies comprises a silicon substrate and a seal ring protruding above a top surface of the first die, a portion of the seal ring being parallel to a sidewall of a first chamfered corner of the first die;

an encapsulant encapsulating the plurality of dies, each bolt of the plurality of bolts extending through the encapsulant; and

a redistribution structure on the plurality of dies and the encapsulant.

15. The semiconductor device of claim 14 , wherein the first chamfered corner of the first die of the plurality of dies has a triangular chamfered surface.

16. The semiconductor device of claim 14 , wherein the first chamfered corner of the first die of the plurality of dies has a quadrilateral chamfered surface.

17. The semiconductor device of claim 16 , wherein the quadrilateral chamfered surface comprises a rectangular shape.

18. The semiconductor device of claim 16 , wherein the quadrilateral chamfered surface comprises a trapezoidal shape.

19. The semiconductor device of claim 14 , wherein the first die of the plurality of dies has chamfered upper sidewalls.

20. The semiconductor device of claim 14 , wherein the first die of the plurality of dies has no more than one chamfered corner.